Spin-based neuron model with domain-wall magnets as synapse M Sharad, C Augustine, G Panagopoulos, K Roy
IEEE Transactions on Nanotechnology 11 (4), 843-853, 2012
213 2012 Low-power functionality enhanced computation architecture using spin-based devices C Augustine, G Panagopoulos, B Behin-Aein, S Srinivasan, A Sarkar, ...
2011 IEEE/ACM International Symposium on Nanoscale Architectures, 129-136, 2011
106 2011 Physics-based SPICE-compatible compact model for simulating hybrid MTJ/CMOS circuits GD Panagopoulos, C Augustine, K Roy
IEEE Transactions on Electron Devices 60 (9), 2808-2814, 2013
96 2013 Write-optimized reliable design of STT MRAM Y Kim, SK Gupta, SP Park, G Panagopoulos, K Roy
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
92 2012 Asymmetrically doped FinFETs for low-power robust SRAMs F Moradi, SK Gupta, G Panagopoulos, DT Wisland, H Mahmoodi, K Roy
IEEE transactions on electron devices 58 (12), 4241-4249, 2011
85 2011 SPICE models for magnetic tunnel junctions based on monodomain approximation X Fong, SH Choday, P Georgios, C Augustine, K Roy
NanoHub, 2013
70 2013 Proposal for neuromorphic hardware using spin devices M Sharad, C Augustine, G Panagopoulos, K Roy
arXiv preprint arXiv:1206.3227, 2012
54 2012 Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation G Panagopoulos, C Augustine, K Roy
69th Device Research Conference, 125-126, 2011
53 2011 A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach G Panagopoulos, C Augustine, K Roy
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
41 2012 A low-power/low-noise readout circuit for integrated capacitive sensors PD Dimitropoulos, DP Karampatzakis, GD Panagopoulos, GI Stamoulis
IEEE Sensors Journal 6 (3), 755-769, 2006
40 2006 Spin neuron for ultra low power computational hardware M Sharad, G Panagopoulos, K Roy
70th Device Research Conference, 221-222, 2012
34 2012 Ultra low energy analog image processing using spin based neurons M Sharad, C Augustine, G Panagopoulos, K Roy
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale …, 2012
29 2012 A compact SPICE model for statistical post-breakdown gate current increase due to TDDB SY Kim, G Panagopoulos, CH Ho, M Katoozi, E Cannon, K Roy
2013 IEEE International Reliability Physics Symposium (IRPS), 2A. 2.1-2A. 2.4, 2013
24 2013 A physical model for grain-boundary-induced threshold voltage variation in polysilicon thin-film transistors CH Ho, G Panagopoulos, K Roy
IEEE transactions on electron devices 59 (9), 2396-2402, 2012
24 2012 Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology F Moradi, G Panagopoulos, G Karakonstantis, D Wisland, H Mahmoodi, ...
2011 IEEE 29th International Conference on Computer Design (ICCD), 326-331, 2011
23 2011 A physics-based three-dimensional analytical model for RDF-induced threshold voltage variations G Panagopoulos, K Roy
IEEE Transactions on Electron Devices 58 (2), 392-403, 2010
22 2010 Cognitive computing with spin-based neural networks M Sharad, C Augustine, G Panagopoulos, K Roy
Proceedings of the 49th Annual Design Automation Conference, 1262-1263, 2012
21 2012 A Three-Dimensional Physical Model for Variations Considering the Combined Effect of NBTI and RDF GD Panagopoulos, K Roy
IEEE transactions on electron devices 58 (8), 2337-2346, 2011
21 2011 Exploring variability and reliability of multi-level STT-MRAM cells G Panagopoulos, C Augustine, X Fong, K Roy
70th Device Research Conference, 139-140, 2012
20 2012 Spin based neuron-synapse module for ultra low power programmable computational networks M Sharad, C Augustine, G Panagopoulos, K Roy
The 2012 International Joint Conference on Neural Networks (IJCNN), 1-7, 2012
20 2012