Single-path nas: Designing hardware-efficient convnets in less than 4 hours D Stamoulis, R Ding, D Wang, D Lymberopoulos, B Priyantha, J Liu, ... Joint European Conference on Machine Learning and Knowledge Discovery in …, 2019 | 109 | 2019 |
NeuralPower: Predict and Deploy Energy-Efficient Convolutional Neural Networks E Cai, DC Juan, D Stamoulis, D Marculescu Asian Conference on Machine Learning, 622-637, 2017 | 51 | 2017 |
Hyperpower: Power-and memory-constrained hyper-parameter optimization for neural networks D Stamoulis, E Cai, DC Juan, D Marculescu 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 19-24, 2018 | 42* | 2018 |
Designing adaptive neural networks for energy-constrained image classification D Stamoulis, TW Chin, AK Prakash, H Fang, S Sajja, M Bognar, ... Proceedings of the International Conference on Computer-Aided Design, 1-8, 2018 | 33 | 2018 |
Hardware-aware machine learning: modeling and optimization D Marculescu, D Stamoulis, E Cai Proceedings of the International Conference on Computer-Aided Design, 1-8, 2018 | 24 | 2018 |
Exploring aging deceleration in FinFET-based multi-core systems E Cai, D Stamoulis, D Marculescu 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 19 | 2016 |
Can we guarantee performance requirements under workload and process variations? D Stamoulis, D Marculescu Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | 14 | 2016 |
Capturing true workload dependency of bti-induced degradation in cpu components D Stamoulis, S Corbetta, D Rodopoulos, P Weckx, P Debacker, BH Meyer, ... 2016 International Great Lakes Symposium on VLSI (GLSVLSI), 373-376, 2016 | 11 | 2016 |
Profit:Priority and Power/Performance Optimization for Many-Core Systems Z Chen, D Stamoulis, D Marculescu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 10 | 2017 |
Efficient reliability analysis of processor datapath using atomistic bti variability models D Stamoulis, D Rodopoulos, BH Meyer, D Soudris, F Catthoor, Z Zilic Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 57-62, 2015 | 10 | 2015 |
Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations D Rodopoulos, D Stamoulis, G Lyras, D Soudris, F Catthoor 2014 IEEE International Conference on IC Design & Technology, 1-4, 2014 | 9 | 2014 |
Single-path mobile automl: Efficient convnet design and nas hyperparameter optimization D Stamoulis, R Ding, D Wang, D Lymberopoulos, B Priyantha, J Liu, ... IEEE Journal of Selected Topics in Signal Processing 14 (4), 609-622, 2020 | 7 | 2020 |
Single-Path NAS: Device-Aware Efficient ConvNet Design D Stamoulis, R Ding, D Wang, D Lymberopoulos, B Priyantha, J Liu, ... arXiv preprint arXiv:1905.04159, 2019 | 6 | 2019 |
Enhancing precipitation models by capturing multivariate and multiscale climate dynamics R Ding, D Stamoulis, K Bhardwaj, D Marculescu, R Marculescu Proceedings of the 3rd International Workshop on Cyber-Physical Systems for …, 2017 | 3 | 2017 |
Linear regression techniques for efficient analysis of transistor variability D Stamoulis, D Rodopoulos, BH Meyer, D Soudris, Z Zilic 2014 21st IEEE international conference on electronics, circuits and systems …, 2014 | 3 | 2014 |
Towards Latency-aware DNN Optimization with GPU Runtime Analysis and Tail Effect Elimination F Yu, Z Xu, T Shen, D Stamoulis, L Shangguan, D Wang, R Madhok, ... arXiv preprint arXiv:2011.03897, 2020 | 1 | 2020 |
Hardware-Aware AutoML for Efficient Deep Learning Applications D Stamoulis PQDT-Global, 2020 | 1 | 2020 |
Learning-based Power and Runtime Modeling for Convolutional Neural Networks E Cai, DC Juan, D Stamoulis, D Marculescu Data Analysis Project, 2019 | 1 | 2019 |
Time-efficient modeling and simulation of true workload dependency for bti-induced degradation in processor-level platform specifications S Corbetta, P Weckx, D Rodopoulos, D Stamoulis, F Catthoor Harnessing Performance Variability in Embedded and High-performance Many …, 2019 | 1 | 2019 |
Efficient variability analysis of arithmetic units using linear regression techniques D Stamoulis, K Tsoumanis, D Rodopoulos, BH Meyer, K Pekmestzi, ... Analog Integrated Circuits and Signal Processing 87 (2), 249-261, 2016 | 1 | 2016 |