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Jaeyoung Kim
Jaeyoung Kim
Senior Circuit Design Engineer at NVIDIA
Verified email at nvidia.com
Title
Cited by
Cited by
Year
A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS
J Kim, P Mazumder
Integration 57, 1-10, 2017
442017
Static random access memory cell having improved write margin for use in ultra-low power application
P Mazumder, JY Kim, N Zheng
US Patent 9,627,042, 2017
202017
Energy-efficient hardware architecture of self-organizing map for ECG clustering in 65-nm CMOS
J Kim, P Mazumder
IEEE Transactions on Circuits and Systems II: Express Briefs 64 (9), 1097-1101, 2017
162017
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS
J Kim, KS Chong, JS Chang, P Mazumder
Proceedings of the 23rd ACM international conference on Great lakes …, 2013
42013
A low-power reconfigurable CMOS power amplifier for wireless sensor network applications
N Zheng, J Kim, P Mazumder
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1086-1089, 2014
32014
Ultra low-power filter bank for hearing aid speech processor
PM Kwen-Siong Chong, Mahmood Barangi, Jaeyoung Kim, Joseph S. Chang
2012 IEEE Subthreshold Microelectronics Conference (SubVT), pp.1-3, 2012
22012
Ultra Low-Power Wireless Sensor Node Design for ECG Sensing Applications
J Kim
12017
Down-Scaled 3D Object for Telediagnostic Imaging Support System
M Lee, HS Shin, SW Yoon, JY Kim
의공학회지 26 (4), 185-191, 2005
12005
Ultra-Low Power Wireless Sensor Network SoC for Biosignal Sensing Application in 65nm CMOS
J Kim, N Zheng, Y Yilmaz, P Mazumder
Proceedings of the 2016 29th International Conference on VLSI Design and …, 2016
2016
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Articles 1–9