Jung Seob Lee
Citata da
Citata da
Improving throughput of power-constrained GPUs using dynamic voltage/frequency and core scaling
J Lee, V Sathisha, M Schulte, K Compton, NS Kim
2011 International Conference on Parallel Architectures and Compilation …, 2011
Optimizing throughput of power-and thermal-constrained multicore processors using DVFS and per-core power-gating
J Lee, NS Kim
2009 46th ACM/IEEE Design Automation Conference, 47-50, 2009
Power management system and method for a processor
JM O'connor, J Lee, M Schulte, S Manne
US Patent App. 13/628,720, 2014
Optimizing total power of many-core processors considering voltage scaling limit and process variations
J Lee, NS Kim
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking
P Aguilera, J Lee, A Farmahini-Farahani, K Morrow, M Schulte, NS Kim
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
Frequency and yield optimization using power gates in power-constrained designs
NS Kim, J Seomun, A Sinkar, J Lee, TH Han, K Choi, Y Shin
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors
D Park, J Lee, NS Kim, T Kim
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 361-364, 2010
Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors
J Lee, ST Zhou, NS Kim
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 229-234, 2010
A Study on Development of Measure System for Weldment Distortion
JH Lee, IS Kim, HK Jang, SK Kwak, JS Kim, HH Na, SH Seong
Proceedings of the Korean Society of Precision Engineering Conference, 677-678, 2010
Design of Robust Low-leakage SRAM Under Process Variations
JS Lee
University of Wisconsin--Madison, 2007
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