Aaron Thean
Citata da
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Vertical GAAFETs for the ultimate CMOS scaling
D Yakimets, G Eneman, P Schuddinck, TH Bao, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 62 (5), 1433-1439, 2015
CMOS vertical multiple independent gate field effect transistor (MIGFET)
L Mathew, Y Du, AVY Thean, M Sadd, A Vandooren, C Parker, ...
2004 IEEE International SOI Conference (IEEE Cat. No. 04CH37573), 187-189, 2004
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, ...
2008 Symposium on VLSI Technology, 88-89, 2008
Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
H Mertens, R Ritzenthaler, A Hikavyy, MS Kim, Z Tao, K Wostyn, SA Chew, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
Heteroepitaxy of InP on Si (001) by selective-area metal organic vapor-phase epitaxy in sub-50 nm width trenches: The role of the nucleation layer and the recess engineering
C Merckling, N Waldron, S Jiang, W Guo, N Collaert, M Caymax, ...
Journal of Applied Physics 115 (2), 023710, 2014
Flash memory: towards single-electronics
VY Aaron, JP Leburton
IEEE Potentials 21 (4), 35-41, 2002
An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates
N Waldron, C Merckling, W Guo, P Ong, L Teugels, S Ansar, ...
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
InGaAs gate-all-around nanowire devices on 300mm Si substrates
N Waldron, C Merckling, L Teugels, P Ong, SAU Ibrahim, F Sebaai, ...
IEEE Electron Device Letters 35 (11), 1097-1099, 2014
Fabrication and Analysis of a Heterojunction Line Tunnel FET
AM Walke, A Vandooren, R Rooyackers, D Leonelli, A Hikavyy, R Loo, ...
IEEE transactions on electron devices 61 (3), 707-715, 2014
32nm general purpose bulk CMOS technology for high performance applications at low voltage
F Arnaud, J Liu, YM Lee, KY Lim, S Kohler, J Chen, BK Moon, CW Lai, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Low temperature deposition of 2D WS 2 layers from WF 6 and H 2 S precursors: impact of reducing agents
A Delabie, M Caymax, B Groven, M Heyne, K Haesevoets, J Meersschaut, ...
Chemical Communications 51 (86), 15692-15695, 2015
Three-dimensional self-consistent simulation of the charging time response in silicon nanocrystal flash memories
JS De Sousa, AV Thean, JP Leburton, VN Freire
Journal of applied physics 92 (10), 6182-6187, 2002
Suitability of high-k gate oxides for III–V devices: A PBTI study in In0.53Ga0.47As devices with Al2O3
J Franco, A Alian, B Kaczer, D Lin, T Ivanov, A Pourghaderi, K Martens, ...
2014 IEEE International Reliability Physics Symposium, 6A. 2.1-6A. 2.6, 2014
Scaling of 32nm low power SRAM with high-K metal gate
HS Yang, R Wong, R Hasumi, Y Gao, NS Kim, DH Lee, S Badrudduza, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Self-heating on bulk FinFET from 14nm down to 7nm node
D Jang, E Bury, R Ritzenthaler, MG Bardon, T Chiarella, K Miyaguchi, ...
2015 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2015
Integration of InGaAs channel n-MOS devices on 200mm Si wafers using the aspect-ratio-trapping technique
N Waldron, G Wang, ND Nguyen, T Orzali, C Merckling, G Brammertz, ...
ECS Transactions 45 (4), 115, 2012
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
F Arnaud, A Thean, M Eller, M Lipinski, YW Teh, M Ostermayr, K Kang, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
A new complementary hetero-junction vertical tunnel-FET integration scheme
R Rooyackers, A Vandooren, AS Verhulst, A Walke, K Devriendt, ...
2013 IEEE International Electron Devices Meeting, 4.2. 1-4.2. 4, 2013
Shell-filling effects and Coulomb degeneracy in planar quantum-dot structures
S Nagaraja, P Matagne, VY Thean, JP Leburton, YH Kim, RM Martin
Physical Review B 56 (24), 15752, 1997
Controlled Sulfurization Process for the Synthesis of Large Area MoS2 Films and MoS2/WS2 Heterostructures
D Chiappe, I Asselberghs, S Sutar, S Iacovo, V Afanas' ev, A Stesmans, ...
Advanced Materials Interfaces 3 (4), 1500635, 2016
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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