| AddNet: Deep neural networks using FPGA-optimized multipliers J Faraone, M Kumm, M Hardieck, P Zipf, X Liu, D Boland, PHW Leong IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (1), 115-128, 2019 | 61 | 2019 |
| A two-speed, radix-4, serial–parallel multiplier DJM Moss, D Boland, PHW Leong IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (4), 769-777, 2018 | 57 | 2018 |
| Training deep neural networks in low-precision with high accuracy using FPGAs S Fox, J Faraone, D Boland, K Vissers, PHW Leong 2019 International Conference on Field-Programmable Technology (ICFPT), 1-9, 2019 | 47 | 2019 |
| FPGA acceleration of multilevel ORB feature extraction for computer vision J Weberruss, L Kleeman, D Boland, T Drummond 2017 27th International Conference on Field Programmable Logic and …, 2017 | 46 | 2017 |
| An FPGA-based implementation of the MINRES algorithm D Boland, GA Constantinides 2008 International Conference on Field Programmable Logic and Applications …, 2008 | 38 | 2008 |
| A block minifloat representation for training deep neural networks S Fox, S Rasoulinezhad, J Faraone, P Leong International Conference on Learning Representations, 2020 | 37 | 2020 |
| Accuracy-performance tradeoffs on an fpga through overclocking K Shi, D Boland, GA Constantinides 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013 | 33 | 2013 |
| Unrolling ternary neural networks S Tridgell, M Kumm, M Hardieck, D Boland, D Moss, P Zipf, PHW Leong ACM Transactions on Reconfigurable Technology and Systems (TRETS) 12 (4), 1-23, 2019 | 32 | 2019 |
| Datapath synthesis for overclocking: Online arithmetic for latency-accuracy trade-offs K Shi, D Boland, E Stott, S Bayliss, GA Constantinides Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 31 | 2014 |
| Customizing low-precision deep neural networks for FPGAs J Faraone, G Gambardella, D Boland, N Fraser, M Blott, PHW Leong 2018 28th International Conference on Field Programmable Logic and …, 2018 | 30 | 2018 |
| Bounding variable values and round-off effects using Handelman representations D Boland, GA Constantinides IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 30 | 2011 |
| Automated precision analysis: A polynomial algebraic approach D Boland, GA Constantinides 2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010 | 30 | 2010 |
| Real-time automatic modulation classification using RFSoC S Tridgell, D Boland, PHW Leong, R Kastner, A Khodamoradi 2020 IEEE International Parallel and Distributed Processing Symposium …, 2020 | 24 | 2020 |
| A scalable approach for automated precision analysis D Boland, GA Constantinides Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012 | 23 | 2012 |
| Efficient FPGA implementation of digit parallel online arithmetic operators K Shi, D Boland, GA Constantinides 2014 International Conference on Field-Programmable Technology (FPT), 115-122, 2014 | 21 | 2014 |
| Real-time FPGA-based anomaly detection for radio frequency signals DJM Moss, D Boland, P Pourbeik, PHW Leong 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 19 | 2018 |
| Hardware-efficient signal generation of layered/enhanced ACO-OFDM for short-haul fiber-optic links Q Wang, B Song, B Corcoran, D Boland, C Zhu, L Zhuang, AJ Lowery Optics Express 25 (12), 13359-13371, 2017 | 19 | 2017 |
| A scalable precision analysis framework D Boland, GA Constantinides IEEE transactions on multimedia 15 (2), 242-256, 2012 | 18 | 2012 |
| Real-time automatic modulation classification S Tridgell, D Boland, PHW Leong, S Siddhartha 2019 International Conference on Field-Programmable Technology (ICFPT), 299-302, 2019 | 15 | 2019 |
| Optimising memory bandwidth use for matrix-vector multiplication in iterative methods D Boland, GA Constantinides International Symposium on Applied Reconfigurable Computing, 169-181, 2010 | 15 | 2010 |
