Bryan Casper
Bryan Casper
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Cited by
Cited by
Portable device and method of communicating medical data information
H Hansen, M Eilersen, N Rolsted
US Patent App. 10/216,680, 2003
An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes
BK Casper, M Haycock, R Mooney
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 2002
A scalable 5–15 Gbps, 14–75 mW low-power I/O transceiver in 65 nm CMOS
G Balamurugan, J Kennedy, G Banerjee, JE Jaussi, M Mansuri, ...
IEEE Journal of Solid-State Circuits 43 (4), 1010-1019, 2008
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew
JE Jaussi, G Balamurugan, DR Johnson, B Casper, A Martin, J Kennedy, ...
IEEE Journal of Solid-State Circuits 40 (1), 80-88, 2005
Differential amplifier offset adjustment
BK Casper, JE Jaussi
US Patent 6,614,301, 2003
Clocking analysis, implementation and measurement techniques for high-speed data links—A tutorial
B Casper, F O'Mahony
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (1), 17-39, 2009
A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.
B Casper, J Jaussi, F O'Mahony, M Mansuri, K Canagasaby, J Kennedy, ...
2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006
A 4710 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS
F O'Mahony, JE Jaussi, J Kennedy, G Balamurugan, M Mansuri, ...
IEEE journal of solid-state circuits 45 (12), 2828-2837, 2010
Modeling and analysis of high-speed I/O links
G Balamurugan, B Casper, JE Jaussi, M Mansuri, F O'Mahony, J Kennedy
IEEE transactions on advanced packaging 32 (2), 237-247, 2009
An 8-Gb/s simultaneous bidirectional link with on-die waveform capture
B Casper, A Martin, JE Jaussi, J Kennedy, R Mooney
IEEE Journal of Solid-State Circuits 38 (12), 2111-2120, 2003
Systems, methods, and apparatuses for stacked memory
B Casper, R Mooney, D Dunning, M Mansuri, JE Jaussi
US Patent 8,612,809, 2013
A scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-lane parallel I/O in 32-nm CMOS
M Mansuri, JE Jaussi, JT Kennedy, TC Hsueh, S Shekhar, ...
IEEE Journal of solid-state circuits 48 (12), 3229-3242, 2013
Wireline receiver circuitry having collaborative timing recovery
T Musah, G Keskin, G Balamurugan, JE Jaussi, BK Casper
US Patent 9,374,250, 2016
Strong Injection Locking in Low-LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver
S Shekhar, M Mansuri, F O'Mahony, G Balamurugan, JE Jaussi, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 56 (8), 1818-1829, 2009
Future microprocessor interfaces: analysis, design and optimization
B Casper, G Balamurugan, JE Jaussi, J Kennedy, M Mansuri, F O'Mahony, ...
2007 IEEE Custom Integrated Circuits Conference, 479-486, 2007
Analysis of PLL clock jitter in high-speed serial links
PK Hanumolu, B Casper, R Mooney, GY Wei, UK Moon
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2003
Information transmission unit
J Jaussi, B Casper, D Comer
US Patent App. 10/335,194, 2004
Decision feedback equalization employing a lookup table
BK Casper
US Patent 6,724,329, 2004
Clock recovery apparatus, method, and system
BK Casper, AK Martin, SR Mooney, JE Jaussi
US Patent 7,457,393, 2008
A 27Gb/s forwarded-clock I/O receiver using an injection-locked LC-DCO in 45nm CMOS
F O'Mahony, S Shekhar, M Mansuri, G Balamurugan, JE Jaussi, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
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