Eduardo de la Torre

Cited by

	All	Since 2018
Citations	2004	765
h-index	24	15
i10-index	56	28

180

135

19992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220238 25 13 12 10 13 27 38 49 48 41 57 87 94 144 152 158 89 132 135 170 156 117 127 60

Public access

View all

46 articles

12 articles

available

not available

Based on funding mandates

Co-authors

Teresa RiesgoUniversidad Politecnica de Madrid / Ministerio de Ciencia, Innovación y UniversidadesVerified email at upm.es
Andres oteroUniversidad Politécnica de Madrid- Centro de Electrónica IndustrialVerified email at upm.es
Jorge PortillaUniversidad Politecnica de MadridVerified email at upm.es
Alfonso RodriguezCentro de Electronica Industrial, Universidad Politecnica de MadridVerified email at upm.es
Javier MoraElectronic engineer, PhD at Universidad Politécnica de MadridVerified email at upm.es
Yago TorrojaProfesor Titular, Universidad Politécnica de MadridVerified email at upm.es
Javier UcedaProfesor UPMVerified email at upm.es
Ruben SalvadorAssociate Professor, Inria - IRISA, CentraleSupélecVerified email at inria.fr
Roberto SarmientoFull Professor, University of Las Palmas de Gran CanariaVerified email at iuma.ulpgc.es
Lukas SekaninaProfessor of Computer Science and Engineering, Brno University of TechnologyVerified email at fit.vutbr.cz
Angel de CastroFull Professor, Universidad Autónoma de MadridVerified email at uam.es
Leonardo SurianoPh.D., Politecnica de MadridVerified email at upm.es
Sebastian LopezAssociate Professor, University of Las Palmas de Gran CanariaVerified email at iuma.ulpgc.es
Rafael ZamacolaUniversidad Politécnica de MadridVerified email at upm.es
Francesca PalumboUNISS - Università degli Studi di SassariVerified email at uniss.it
Arturo Pérez GarcíaCentro de Electrónica Industrial, Universidad Politécnica de MadridVerified email at upm.es
maxime pelcatINSA de Rennes, IETRVerified email at insa-rennes.fr
Teresa CerveroBarcelona Supercomputing Center (BSC-CNS)Verified email at bsc.es
Peter LangendoerferDepartment Head Wireless Systems (IHP) /Professor /Chair Wireless SystemsVerified email at ihp-microelectronics.com
Gustavo Marrero CallicoFull Professor, University of Las Palmas de Gran CanariaVerified email at iuma.ulpgc.es

Eduardo de la Torre

Universidad Politécnica de Madrid

Verified email at upm.es

FPGAs Reconfigurable systems Evolvable hardware Sensor networks digital signal processing


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Design methodologies based on hardware description languages T Riesgo, Y Torroja, E De la Torre IEEE Transactions on Industrial electronics 46 (1), 3-12, 1999	135	1999
A modular architecture for nodes in wireless sensor networks. J Portilla, A De Castro, E De La Torre, T Riesgo J. Univers. Comput. Sci. 12 (3), 328-339, 2006	108	2006
Embedded runtime reconfigurable nodes for wireless sensor networks applications YE Krasteva, J Portilla, E de la Torre, T Riesgo IEEE Sensors Journal 11 (9), 1800-1810, 2011	86	2011
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework A Rodríguez, J Valverde, J Portilla, A , Otero, T Riesgo, E de la Torre Sensors 18 (6), 1-30, 2018	79	2018
Using SRAM based FPGAs for power-aware high performance wireless sensor networks J Valverde, A Otero, M Lopez, J Portilla, E De la Torre, T Riesgo Sensors 12 (3), 2667-2692, 2012	71	2012
Adaptable security in wireless sensor networks by using reconfigurable ECC hardware coprocessors J Portilla, A Otero, E de la Torre, T Riesgo, O Stecklina, S Peter, ... International Journal of Distributed Sensor Networks 6 (1), 740823, 2010	64	2010
Virtex II FPGA bitstream manipulation: Application to reconfiguration control systems YE Krasteva, E De La Torre, T Riesgo, D Joly 2006 International Conference on Field Programmable Logic and Applications, 1-4, 2006	62	2006
Self-reconfigurable Evolvable Hardware System for Adaptive Image Processing R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina Transactions on Computers, 1-1, 2013	61	2013
Fault tolerance analysis and self-healing strategy of autonomous, evolvable hardware systems R Salvador, A Otero, J Mora, E de la Torre, L Sekanina, T Riesgo 2011 International Conference on Reconfigurable Computing and FPGAs, 164-169, 2011	57	2011
FPGAs: fundamentals, advanced features, and applications in industrial electronics JJR Andina, E De la Torre Arnanz, MDV Peña CRC Press, 2017	54	2017
Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs YE Krasteva, AB Jimeno, E de la Torre, T Riesgo 16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 77-83, 2005	53	2005
A fast emulation-based NoC prototyping framework YE Krasteva, F Criado, E de la Torre, T Riesgo 2008 International Conference on Reconfigurable Computing and FPGAs, 211-216, 2008	51	2008
Remote HW-SW reconfigurable wireless sensor nodes YE Krasteva, J Portilla, JM Carnicer, E de la Torre, T Riesgo Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE …, 2008	49	2008
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems A Otero, E de la Torre, T Riesgo 2012 International Conference on Reconfigurable Computing and FPGAs, 1-8, 2012	43	2012
Cross-layer design of reconfigurable cyber-physical systems M Masin, F Palumbo, H Myrhaug, JA de Oliveira Filho, M Pastena, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017	33	2017
Automatic generation of identical routing pairs for FPGA implemented DPL logic W He, A Otero, E de la Torre, T Riesgo 2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012	33	2012
A precharge-absorbed DPL logic for reducing early propagation effects on FPGA implementations W He, E de la Torre, T Riesgo 2011 International Conference on Reconfigurable Computing and FPGAs, 217-222, 2011	32	2011
Scalable hardware-based on-board processing for run-time adaptive lossless hyperspectral compression A Rodriguez, L Santos, R Sarmiento, E De La Torre IEEE Access 7, 10644-10652, 2019	31	2019
A Modular Peripheral to Support Self-Reconfiguration in SoCs A Otero, Á Morales-Cas, J Portilla, E de la Torre, T Riesgo Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th …, 2010	29	2010
Run-time reconfigurable MPSoC-based on-board processor for vision-based space navigation A Pérez, A Rodríguez, A Otero, DG Arjona, A Jiménez-Peralo, ... IEEE Access 8, 59891-59905, 2020	28	2020

The system can't perform the operation now. Try again later.

Articles 1–20

Citations per year

Duplicate citations

Merged citations

Add co-authorsCo-authors

Follow

Cited by

Co-authors