Eduardo de la Torre
Titolo
Citata da
Citata da
Anno
Design methodologies based on hardware description languages
T Riesgo, Y Torroja, E De la Torre
IEEE Transactions on Industrial electronics 46 (1), 3-12, 1999
1241999
A modular architecture for nodes in wireless sensor networks.
J Portilla, A De Castro, E De La Torre, T Riesgo
J. UCS 12 (3), 328-339, 2006
942006
Embedded runtime reconfigurable nodes for wireless sensor networks applications
YE Krasteva, J Portilla, E de la Torre, T Riesgo
IEEE Sensors Journal 11 (9), 1800-1810, 2011
802011
Using SRAM based FPGAs for power-aware high performance wireless sensor networks
J Valverde, A Otero, M Lopez, J Portilla, E De la Torre, T Riesgo
Sensors 12 (3), 2667-2692, 2012
592012
Adaptable security in wireless sensor networks by using reconfigurable ECC hardware coprocessors
J Portilla, A Otero, E de la Torre, T Riesgo, O Stecklina, S Peter, ...
International Journal of Distributed Sensor Networks 6 (1), 740823, 2010
592010
Virtex II FPGA bitstream manipulation: Application to reconfiguration control systems
YE Krasteva, E De La Torre, T Riesgo, D Joly
2006 International Conference on Field Programmable Logic and Applications, 1-4, 2006
592006
Self-reconfigurable Evolvable Hardware System for Adaptive Image Processing
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
Transactions on Computers, 1-1, 2013
582013
A fast emulation-based NoC prototyping framework
YE Krasteva, F Criado, E de la Torre, T Riesgo
2008 International Conference on Reconfigurable Computing and FPGAs, 211-216, 2008
502008
Remote HW-SW reconfigurable wireless sensor nodes
YE Krasteva, J Portilla, JM Carnicer, E de la Torre, T Riesgo
Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE …, 2008
472008
Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs
YE Krasteva, AB Jimeno, E de la Torre, T Riesgo
16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 77-83, 2005
472005
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework
A Rodríguez, J Valverde, J Portilla, A , Otero, T Riesgo, E de la Torre
Sensors 18 (6), 1-30, 2018
432018
Fault tolerance analysis and self-healing strategy of autonomous, evolvable hardware systems
R Salvador, A Otero, J Mora, E de la Torre, L Sekanina, T Riesgo
2011 International Conference on Reconfigurable Computing and FPGAs, 164-169, 2011
422011
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems
A Otero, E de la Torre, T Riesgo
2012 International Conference on Reconfigurable Computing and FPGAs, 1-8, 2012
392012
FPGAs: fundamentals, advanced features, and applications in industrial electronics
JJR Andina, E De la Torre Arnanz, MD Valdes
CRC Press, 2017
372017
Automatic generation of identical routing pairs for FPGA implemented DPL logic
W He, A Otero, E de la Torre, T Riesgo
2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012
302012
A precharge-absorbed DPL logic for reducing early propagation effects on FPGA implementations
W He, E de la Torre, T Riesgo
2011 International Conference on Reconfigurable Computing and FPGAs, 217-222, 2011
302011
Cross-layer design of reconfigurable cyber-physical systems
M Masin, F Palumbo, H Myrhaug, JA de Oliveira Filho, M Pastena, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
282017
A Modular Peripheral to Support Self-Reconfiguration in SoCs
A Otero, Á Morales-Cas, J Portilla, E de la Torre, T Riesgo
Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th …, 2010
272010
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems
A Otero, R Salvador, J Mora, E de la Torre, T Riesgo, L Sekanina
2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 336-343, 2011
252011
An interleaved EPE-immune PA-DPL structure for resisting concentrated EM side channel attacks on FPGA implementation
W He, E de la Torre, T Riesgo
International Workshop on Constructive Side-Channel Analysis and Secure …, 2012
242012
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
Articoli 1–20