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Yong-Bin Kim
Yong-Bin Kim
Northeastern University, University of Utah, SUN Microsystems, HP, Intel
Verified email at ece.neu.edu - Homepage
Title
Cited by
Cited by
Year
CNTFET-based design of ternary logic gates and arithmetic circuits
S Lin, YB Kim, F Lombardi
IEEE transactions on nanotechnology 10 (2), 217-225, 2009
4982009
Challenges for nanoscale MOSFETs and emerging nanoelectronics
YB Kim
Transactions on Electrical and Electronic Materials 11 (3), 93-105, 2010
2712010
A novel CNTFET-based ternary logic gate design
S Lin, YB Kim, F Lombardi
2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 435-438, 2009
1772009
Design of a ternary memory cell using CNTFETs
S Lin, YB Kim, F Lombardi
IEEE transactions on nanotechnology 11 (5), 1019-1025, 2012
1462012
A novel design methodology to optimize the speed and power of the CNTFET circuits
YB Kim, YB Kim, F Lombardi
2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 1130 …, 2009
1222009
Design of a CNTFET-based SRAM cell by dual-chirality selection
S Lin, YB Kim, F Lombardi
IEEE Transactions on Nanotechnology 9 (1), 30-37, 2009
1092009
A CMOS subbandgap reference circuit with 1-V power supply voltage
J Doyle, YJ Lee, YB Kim, H Wilsch, F Lombardi
IEEE Journal of Solid-State Circuits 39 (1), 252-255, 2004
1082004
Standby leakage power reduction technique for nanoscale CMOS VLSI systems
HJ Jeon, YB Kim, M Choi
IEEE transactions on instrumentation and measurement 59 (5), 1127-1133, 2010
1022010
Analysis and design of nanoscale CMOS storage elements for single-event hardening with multiple-node upset
S Lin, YB Kim, F Lombardi
IEEE Transactions on Device and Materials Reliability 12 (1), 68-77, 2011
982011
Performance evaluation of CNFET-based logic gates
G Cho, YB Kim, F Lombardi, MS Choi
2009 IEEE Instrumentation and Measurement Technology Conference, 909-912, 2009
982009
Leakage minimization technique for nanoscale CMOS VLSI
KK Kim, YB Kim, M Choi, N Park
IEEE Design & Test of Computers 24 (4), 322-330, 2007
902007
A CMOS low-power low-offset and high-speed fully dynamic latched comparator
HJ Jeon, YB Kim
23rd IEEE International SOC Conference, 285-288, 2010
852010
Design and performance evaluation of radiation hardened latches for nanoscale CMOS
S Lin, YB Kim, F Lombardi
IEEE transactions on very large scale integration (VLSI) systems 19 (7 …, 2010
802010
Fault tolerant source routing for network-on-chip
YB Kim, YB Kim
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007
792007
A new SRAM cell design using CNTFETs
S Lin, YB Kim, F Lombardi, YJ Lee
2008 International SoC Design Conference 1, I-168-I-171, 2008
782008
A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator
HJ Jeon, YB Kim
Analog Integrated Circuits and Signal Processing 70 (3), 337-346, 2012
762012
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability
S Lin, YB Kim, F Lombardi
Integration 43 (2), 176-187, 2010
712010
A 11-transistor nanoscale CMOS memory cell for hardening to soft errors
S Lin, YB Kim, F Lombardi
IEEE transactions on very large scale integration (VLSI) systems 19 (5), 900-904, 2010
682010
Soft-error hardening designs of nanoscale CMOS latches
S Lin, YB Kim, F Lombardi
2009 27th IEEE VLSI Test Symposium, 41-46, 2009
632009
A novel adaptive design methodology for minimum leakage power considering PVT variations on nanoscale VLSI systems
KK Kim, YB Kim
IEEE transactions on very large scale integration (VLSI) systems 17 (4), 517-528, 2009
612009
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