Weicheng Liu
Titolo
Citata da
Citata da
Anno
Design methodology for voltage-scaled clock distribution networks
C Sitik, W Liu, B Taskin, E Salman
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10…, 2016
252016
Enhanced level shifter for multi-voltage operation
W Liu, E Salman, C Sitik, B Taskin
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1442-1445, 2015
122015
A novel static D-flip-flop topology for low swing clocking
M Rathore, W Liu, E Salman, C Sitik, B Taskin
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 301-306, 2015
82015
Clock skew scheduling in the presence of heavily gated clock networks
W Liu, E Salman, C Sitik, B Taskin
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 283-288, 2015
72015
SLECTS: Slew-driven clock tree synthesis
W Liu, C Sitik, E Salman, B Taskin, S Sundareswaran, B Huang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (4), 864-874, 2019
42019
Exploiting useful skew in gated low voltage clock trees
W Liu, E Salman, C Sitik, B Taskin
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2595-2598, 2016
42016
Circuits and algorithms to facilitate low swing clocking in nanoscale technologies
W Liu, E Salman, C Sitik, B Taskin, S Sundareswaran, B Huang
Proceedings of Semiconductor Research Corporation (SRC) TECHCON. SRC, 2015
22015
Low Voltage Clock Tree Synthesis with Local Gate Clusters
C Sitik, W Liu, B Taskin, E Salman
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 99-104, 2019
12019
Slew-driven clock tree synthesis
WC Liu, E Salman, AC Sitik, B Taskin
US Patent 10,338,633, 2019
2019
Low Voltage Clocking Methodologies for Nanoscale ICs
W Liu
State University of New York at Stony Brook, 2018
2018
Il sistema al momento non pu eseguire l'operazione. Riprova pi tardi.
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