Alberto Ros
Alberto Ros
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Cited by
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
B Cuesta, A Ros, ME Gómez, A Robles, J Duato
2011 38th Annual International Symposium on Computer Architecture (ISCA), 93-103, 2011
Complexity-effective multicore coherence
A Ros, S Kaxiras
Proceedings of the 21st international conference on Parallel architectures …, 2012
System and method for simplifying cache coherence using multiple write policies
S Kaxiras, A Ros
US Patent 9,274,960, 2016
A new perspective for efficient virtual-cache coherence
S Kaxiras, A Ros
Proceedings of the 40th Annual International Symposium on Computer …, 2013
Splash-3: A properly synchronized benchmark suite for contemporary research
C Sakalis, C Leonardsson, S Kaxiras, A Ros
2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016
A direct coherence protocol for many-core chip multiprocessors
A Ros, ME Acacio, JM Garcia
IEEE Transactions on Parallel and Distributed Systems 21 (12), 1779-1792, 2010
DiCo-CMP: Efficient cache coherency in tiled CMP architectures
A Ros, ME Acacio, JM García
2008 IEEE International Symposium on Parallel and Distributed Processing, 1-11, 2008
Efficient invisible speculative execution through selective delay and value prediction
C Sakalis, S Kaxiras, A Ros, A Jimborean, M Själander
2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture …, 2019
Increasing the effectiveness of directory caches by avoiding the tracking of noncoherent memory blocks
B Cuesta, A Ros, ME Gomez, A Robles, J Duato
IEEE Transactions on Computers 62 (3), 482-495, 2011
Scalable Directory Organization for Tiled CMP Architectures.
A Ros, ME Acacio, JM García
CDES 8, 112-118, 2008
Turning centralized coherence and distributed critical-section execution on their head: A new approach for scalable distributed shared memory
S Kaxiras, D Klaftenegger, M Norgren, A Ros, K Sagonas
Proceedings of the 24th International Symposium on High-Performance Parallel …, 2015
Hierarchical private/shared classification: the key to simple and efficient coherence for clustered cache hierarchies
A Ros, M Davari, S Kaxiras
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
Cache Coherence Protocols for Many-Core CMPs
A Ros, ME Acacio, JM Garcıa
Parallel and Distributed Computing, 93-118, 2010
Temporal-aware mechanism to detect private data in chip multiprocessors
A Ros, B Cuesta, ME Gómez, A Robles, J Duato
2013 42nd International Conference on Parallel Processing, 562-571, 2013
Self-related traces: An alternative to full-system simulation for NoCs
F Trivino, FJ Andujar, FJ Alfaro, JL Sánchez, A Ros
2011 International Conference on High Performance Computing & Simulation …, 2011
Building heterogeneous unified virtual memories (uvms) without the overhead
K Koukos, A Ros, E Hagersten, S Kaxiras
ACM Transactions on Architecture and Code Optimization (TACO) 13 (1), 1-22, 2016
Callback: Efficient synchronization without invalidation with a directory just for spin-waiting
A Ros, S Kaxiras
2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture …, 2015
Ascib: Adaptive selection of cache indexing bits for removing conflict misses
A Ros, P Xekalakis, M Cintra, ME Acacio, JM García
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
Non-speculative load-load reordering in TSO
A Ros, TE Carlson, M Alipour, S Kaxiras
ACM SIGARCH Computer Architecture News 45 (2), 187-200, 2017
A novel lightweight directory architecture for scalable shared-memory multiprocessors
A Ros, ME Acacio, JM García
European Conference on Parallel Processing, 582-591, 2005
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