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Deshanand Singh
Deshanand Singh
Email verificata su intel.com
Titolo
Citata da
Citata da
Anno
From OpenCL to high-performance hardware on FPGAs
TS Czajkowski, U Aydonat, D Denisenko, J Freeman, M Kinsner, D Neto, ...
22nd international conference on field programmable logic and applications …, 2012
3402012
Gzip on a chip: High performance lossless data compression on fpgas using opencl
MS Abdelfattah, A Hagiescu, D Singh
Proceedings of the international workshop on openCL 2013 & 2014, 1-9, 2014
1382014
Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms
D Chen, D Singh
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 297-304, 2013
1052013
FPGA technology mapping: a study of optimality
A Ling, DP Singh, SD Brown
Proceedings of the 42nd annual Design Automation Conference, 427-432, 2005
982005
Integrated retiming and placement for field programmable gate arrays
DP Singh, SD Brown
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field …, 2002
892002
The case for registered routing switches in field programmable gate arrays
DP Singh, SD Brown
Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field …, 2001
692001
Using OpenCL to evaluate the efficiency of CPUs, GPUs and FPGAs for information filtering
D Chen, D Singh
22nd International Conference on Field Programmable Logic and Applications …, 2012
672012
Implementing FPGA design with the OpenCL standard
D Singh
Altera whitepaper 1, 2011
602011
Incremental retiming for FPGA physical synthesis
DP Singh, V Manohararajah, SD Brown
Proceedings of the 42nd annual Design Automation Conference, 433-438, 2005
492005
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
D Chen, D Singh, J Chromczak, D Lewis, R Fung, D Neto, V Betz
Proceedings of the 18th annual ACM/SIGDA international symposium on Field …, 2010
452010
FPGA logic synthesis using quantified boolean satisfiability
A Ling, DP Singh, SD Brown
Theory and Applications of Satisfiability Testing: 8th International …, 2005
452005
Incremental placement for layout driven optimizations on FPGAs
DP Singh, SD Brown
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
442002
OpenCL for FPGAs: Prototyping a compiler
TS Czajkowski, D Neto, M Kinsner, U Aydonat, J Wong, D Denisenko, ...
Proceedings of the International Conference on Engineering of Reconfigurable …, 2012
432012
Configuring a programmable device using high-level language
DTL Chen, D Singh
US Patent 8,959,469, 2015
422015
Constrained clock shifting for field programmable gate arrays
DP Singh, SD Brown
Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field …, 2002
392002
Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines
I Blunno, GR Chiu, D Singh, V Manohararajah, SD Brown
US Patent 7,500,216, 2009
322009
Harnessing the power of FPGAs using Altera's OpenCL compiler
DP Singh, TS Czajkowski, A Ling
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013
282013
Programmable logic devices with skewed clocking signals
D Singh, A Hall
US Patent 7,107,477, 2006
282006
Method and apparatus for placement of components onto programmable logic devices
DP Singh, SD Brown, TP Borer, C Sanford, G Quan
US Patent 6,779,169, 2004
272004
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow
V Manohararajah, GR Chiu, DP Singh, SD Brown
Proceedings of the 2006 international workshop on System-level interconnect …, 2006
262006
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
Articoli 1–20