Ramiro Taco
Ramiro Taco
Verified email at dimes.unical.it
Title
Cited by
Cited by
Year
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
R Taco, I Levi, M Lanuzza, A Fish
Solid-State Electronics 117, 185-192, 2016
392016
Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design
R Taco, I Levi, A Fish, M Lanuzza
2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel …, 2014
192014
An 88-fJ/40-MHz [0.4 V]–0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI
R Taco, I Levi, M Lanuzza, A Fish
IEEE Journal of Solid-State Circuits 54 (2), 560-568, 2018
162018
Dynamic gate-level body biasing for subthreshold digital design
M Lanuzza, R Taco, D Albano
2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014
132014
Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology
R Taco, I Levi, M Lanuzza, A Fish
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 41-44, 2016
122016
Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines
D Albano, M Lanuzza, R Taco, F Crupi
International Journal of Circuit Theory and Applications 43 (11), 1523-1540, 2015
102015
Evaluation of dual mode logic in 28nm FD-SOI technology
R Taco, I Levi, M Lanuzza, A Fish
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
82017
Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits.
R Taco, M Lanuzza, D Albano
VLSI Design, 2015
62015
Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI
R Taco, I Levi, M Lanuzza, A Fish
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2015
42015
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths
I Stanger, N Shavit, R Taco, M Lanuzza, A Fish
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1639-1643, 2020
32020
A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16× 16-b Booth Multiplier in 16-nm FinFET
N Shavit, I Stanger, R Taco, M Lanuzza, A Fish
IEEE Solid-State Circuits Letters 3, 314-317, 2020
32020
Process variation-aware datapath employing dual mode logic
N Shavit, I Stanger, R Taco, A Fish
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
32018
Dual Mode Logic Address Decoder
L Yavits, R Taco, N Shavit, I Stanger, A Fish
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
22020
Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications
E Garzón, B Zambrano, T Moposita, R Taco, LM Prócel, L Trojman
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2020
22020
Efficiency of dual mode logic in nanoscale technology nodes
N Shavit, R Taco, A Fish
2018 IEEE International Conference on the Science of Electrical Engineering …, 2018
22018
Improving speed and power characteristics of pulse-triggered flip-flops
M Lanuzza, R Taco
2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014
22014
Live Demonstration: A 0.8 V, 1.54 pJ/940 MHz Dual Mode Logic-based 16x16-bit Booth Multiplier in 16-nm FinFET
N Shavit, I Stanger, R Taco, M Lanuzza, A Fish
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2021
2021
Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths
I Stanger, N Shavit, R Taco, M Lanuzza, A Fish
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-1, 2021
2021
RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies
L Trojman, D Rivadeneira, M Villegas, E Acurio, M Lanuzza, LM Procel, ...
IEEE LASCAS 2021, 2021
2021
High-Speed and Low-Energy Dual-Mode Logic based Single-Clock-Cycle Binary Comparator
R Escobar, LM Procel, L Trojman, M Lanuzza, R Taco
IEEE LASCAS 2021, 2021
2021
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