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Yun R. Qu
Yun R. Qu
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High-performance and Dynamically Updatable Packet Classification Engine on FPGA
YR Qu, V Prasanna
IEEE Transactions on Parallel and Distributed Systems (TPDS), 2015
932015
Accelerating decision tree based traffic classification on FPGA and multicore platforms
D Tong, YR Qu, VK Prasanna
IEEE transactions on parallel and distributed systems 28 (11), 3046-3059, 2017
842017
Optimizing many-field packet classification on FPGA, multi-core general purpose processor, and GPU
YR Qu, HH Zhang, S Zhou, VK Prasanna
2015 ACM/IEEE Symposium on Architectures for Networking and Communications …, 2015
542015
Handbook on Data Centers
Khan, S Ullah, Zomaya, AY Eds.
Springer, 2015
512015
High-performance Architecture for Dynamically Updatable Packet Classification on FPGA
YR Qu, S Zhou, V Prasanna
ACM/IEEE Symposium on Architectures for Networking and Communications …, 2013
472013
Scalable Many-field Packet Classification on Multi-core Processors
YR Qu, S Zhou, V Prasanna
International Symposium on Computer Architecture and High Performance …, 2013
352013
A Decomposition-based Approach for Scalable Many-field Packet Classification on Multi-core Processors
YR Qu, S Zhou, V Prasanna
International Journal of Parallel Programming (IJPP), 1-23, 2014
232014
Scalable and dynamically updatable lookup engine for decision-trees on FPGA
YR Qu, VK Prasanna
IEEE High Performance Extreme Computing Conference (HPEC '14), 1-6, 2014
212014
Multi-core Implementation of Decomposition-based Packet Classification Algorithms
S Zhou, YR Qu, V Prasanna
International Conference on Parallel Computing Techniques (PaCT '13), 2013
212013
Multi-core Implementation of Decomposition-based Packet Classification Algorithms
S Zhou, YR Qu, V Prasanna
Journal of Supercomputing 7979, 105-119, 2013
212013
High-throughput traffic classification on multi-core processors
D Tong, YR Qu, V Prasanna
International Conference on High Performance Switching and Routing (HPSR '14 …, 2014
162014
High-performance Pipelined Architecture for Tree-based IP lookup Engine on FPGA
YR Qu, V Prasanna
Reconfigurable Architectures Workshop (RAW '13), 2013
162013
Large-scale packet classification on FPGA
S Zhou, YR Qu, VK Prasanna
2015 IEEE 26th International Conference on Application-specific Systems …, 2015
132015
Compact Hash Tables for High-performance Traffic Classification on Multi-core Processors
YR Qu, V Prasanna
IEEE International Symposium on Computer Architecture and High Performance …, 2014
132014
Enabling high throughput and virtualization for traffic classification on FPGA
YR Qu, VK Prasanna
2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015
112015
Fast Dynamically Updatable Packet Classifier on FPGA
YR Qu, V Prasanna
International Conference on Field Programmable Logic and Applications (FPL '13), 2013
102013
A distributed cooperative product code for multi-source multi-relay single-destination wireless network
Z Xia, Y Qu, H Yu, Y Xu
2009 15th Asia-Pacific Conference on Communications, 736-739, 2009
102009
High-Throughput Hash-based Online Traffic Classification Engines on FPGA
VR Gandhi, YR Qu, V Prasanna
International Conference on Reconfigurable Computing and FPGAs (ReConfig '14), 2014
82014
Large-scale Multi-flow Regular Expression Matching on FPGA
YR Qu, YHE Yang, V Prasanna
IEEE Conference on High Performance Switching and Routing (HPSR '12), 2012
72012
Architecture and Performance Models for Scalable IP Lookup Engines on FPGA
YHE Yang, YR Qu, S Haria, V Prasanna
International Conference on High Performance Switching and Routing (HPSR '13), 2013
62013
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