| Multi-objective mapping for mesh-based NoC architectures G Ascia, V Catania, M Palesi Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware …, 2004 | 271 | 2004 |
| Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip G Ascia, V Catania, M Palesi, D Patti IEEE Transactions on Computers 57 (6), 809-820, 2008 | 246 | 2008 |
| Multi-objective design space exploration using genetic algorithms M Palesi, T Givargis Proceedings of the tenth international symposium on Hardware/software …, 2002 | 204 | 2002 |
| Application specific routing algorithms for networks on chip M Palesi, R Holsmark, S Kumar, V Catania IEEE Transactions on Parallel and Distributed Systems 20 (3), 316-330, 2008 | 201 | 2008 |
| Noxim: Network-on-chip simulator F Fazzino, M Palesi, D Patti URL: http://sourceforge. net/projects/noxim 13, 2008 | 189 | 2008 |
| Noxim: An open, extensible and cycle-accurate network on chip simulator V Catania, A Mineo, S Monteleone, M Palesi, D Patti 2015 IEEE 26th international conference on application-specific systems …, 2015 | 179 | 2015 |
| Cycle-accurate network on chip simulation with noxim V Catania, A Mineo, S Monteleone, M Palesi, D Patti ACM Transactions on Modeling and Computer Simulation (TOMACS) 27 (1), 1-25, 2016 | 156 | 2016 |
| A methodology for design of application specific deadlock-free routing algorithms for NoC systems V Catania, R Holsmark, S Kumar, M Palesi Proceedings of the 4th International Conference on Hardware/Software …, 2006 | 115 | 2006 |
| Efficient design space exploration for application specific systems-on-a-chip G Ascia, V Catania, AG Di Nuovo, M Palesi, D Patti Journal of Systems Architecture 53 (10), 733-750, 2007 | 108 | 2007 |
| Routing algorithms in networks-on-chip M Palesi, M Daneshtalab Springer, 2014 | 103 | 2014 |
| Region-based routing: a mechanism to support efficient routing algorithms in NoCs A Mejia, M Palesi, J Flich, S Kumar, P López, R Holsmark, J Duato IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (3), 356-369, 2009 | 92 | 2009 |
| Data encoding schemes in networks on chip M Palesi, G Ascia, F Fazzino, V Catania IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 86 | 2011 |
| HARAQ: Congestion-aware learning model for highly adaptive routing algorithm in on-chip networks M Ebrahimi, M Daneshtalab, F Farahnakian, J Plosila, P Liljeberg, ... 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 19-26, 2012 | 82 | 2012 |
| A GA-based design space exploration framework for parameterized system-on-a-chip platforms G Ascia, V Catania, M Palesi IEEE Transactions on Evolutionary Computation 8 (4), 329-346, 2004 | 72 | 2004 |
| Data encoding techniques for reducing energy consumption in network-on-chip N Jafarzadeh, M Palesi, A Khademzadeh, A Afzali-Kusha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (3), 675-685, 2013 | 65 | 2013 |
| A method for router table compression for application specific routing in mesh topology NoC architectures M Palesi, S Kumar, R Holsmark International Workshop on Embedded Computer Systems, 373-384, 2006 | 65 | 2006 |
| A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. G Ascia, V Catania, M Palesi J. UCS 12 (4), 370-394, 2006 | 61 | 2006 |
| EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration. G Ascia, V Catania, M Palesi, D Patti ESTImedia, 65-72, 2003 | 53 | 2003 |
| Neighbors-on-path: A new selection strategy for on-chip networks G Ascia, V Catania, M Palesi, D Patti 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia, 79-84, 2006 | 48 | 2006 |
| Mapping cores on network-on-chip G Ascia, V Catania, M Palesi International Journal of Computational Intelligence Research 1 (1), 109-126, 2005 | 48 | 2005 |
Davide PattiUniversity of CataniaVerified email at dieei.unict.it
