Tsa-net: Tube self-attention network for action quality assessment S Wang, D Yang, P Zhai, C Chen, L Zhang
Proceedings of the 29th ACM international conference on multimedia, 4902-4910, 2021
46 2021 A high-linearity pipelined ADC with opamp split-sharing in a combined front-end of S/H and MDAC1 Z Wang, M Wang, W Gu, C Chen, F Ye, J Ren
IEEE Transactions on Circuits and Systems I: Regular Papers 60 (11), 2834-2844, 2013
31 2013 OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators C Chen, H Ding, H Peng, H Zhu, R Ma, P Zhang, X Yan, Y Wang, M Wang, ...
ESSCIRC 2017-43rd IEEE European solid state circuits conference, 259-262, 2017
30 2017 A 4T2R RRAM bit cell for highly parallel ternary content addressable memory X Wang, L Wang, Y Wang, J An, C Dou, Z Wu, X Zhang, J Liu, C Zhang, ...
IEEE Transactions on Electron Devices 68 (10), 4933-4937, 2021
24 2021 A 91.0-dB SFDR single-coarse dual-fine pipelined-SAR ADC with split-based background calibration in 28-nm CMOS Y Cao, S Zhang, T Zhang, Y Chen, Y Zhao, C Chen, F Ye, J Ren
IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 641-654, 2020
20 2020 COMB-MCM: Computing-on-memory-boundary NN processor with bipolar bitwise sparsity optimization for scalable multi-chiplet-module edge machine learning H Zhu, B Jiao, J Zhang, X Jia, Y Wang, T Guan, S Wang, D Niu, H Zheng, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022
19 2022 Transformer-based varactor-less 96GHz–110GHz VCO and 89GHz–101GHz QVCO in 65nm CMOS X Liu, C Chen, J Ren, HC Luong
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 357-360, 2016
19 2016 OCEAN: An on-chip incremental-learning enhanced artificial neural network processor with multiple gated-recurrent-unit accelerators C Chen, H Ding, H Peng, H Zhu, Y Wang, CJR Shi
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (3 …, 2018
18 2018 Machine learning based prior-knowledge-free calibration for split pipelined-SAR ADCs with open-loop amplifiers achieving 93.7-dB SFDR T Zhang, Y Cao, S Zhang, C Chen, F Ye, J Ren
ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019
17 2019 16.2 A 28nm 53.8 TOPS/W 8b sparse transformer accelerator with in-memory butterfly zero skipper for unstructured-pruned NN and CIM-based local-attention-reusable engine S Liu, P Li, J Zhang, Y Wang, H Zhu, W Jiang, S Tang, C Chen, Q Liu, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 250-252, 2023
14 2023 A 9-Bit Resistor-Based Highly Digital Temperature Sensor With a SAR-Quantization Embedded Differential Low-Pass Filter in 65-nm CMOS With a 2.5- A Wang, C Chen, C Liu, CJR Shi
IEEE Sensors Journal 19 (17), 7215-7225, 2019
14 2019 A 14-bit 200-MS/s time-interleaved ADC with sample-time error calibration Y Zhang, C Chen, B Yu, F Ye, J Ren
Journal of Semiconductors 33 (10), 105010, 2012
13 2012 A 14-bit 200-MS/s time-interleaved ADC calibrated with LMS-FIR and interpolation filter F Ye, P Zhang, B Yu, C Chen, Y Zhu, J Ren
2011 IEEE International Conference of Electron Devices and Solid-State …, 2011
13 2011 A communication-aware dnn accelerator on imagenet using in-memory entry-counting based algorithm-circuit-architecture co-design in 65-nm cmos H Zhu, C Chen, S Liu, Q Zou, M Wang, L Zhang, X Zeng, CJR Shi
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 10 (3 …, 2020
12 2020 Design and analysis of an always-ON input-biased pA-current sub-nW mV-threshold hysteretic comparator for near-zero energy sensing A Wang, C Chen, CR Shi
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2284-2294, 2017
12 2017 An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system H Chen, J Xiang, X Xue, C Chen, F Ye, J Xu, J Ren
Journal of Semiconductors 35 (11), 115008, 2014
10 2014 IFPNA: A flexible and efficient deep learning processor in 28-nm CMOS using a domain-specific instruction set and reconfigurable fabric C Chen, X Liu, H Peng, H Ding, CJR Shi
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (2 …, 2019
9 2019 A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier C Chen, Z Feng, H Chen, M Wang, J Xu, F Ye, J Ren
2014 IEEE International Symposium on circuits and systems (ISCAS), 2361-2364, 2014
9 2014 A mixed sample-time error calibration technique in time-interleaved ADCs B Yu, C Chen, F Ye, J Ren
IEICE Electronics Express 10 (24), 20130882-20130882, 2013
9 2013 A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation B Yu, C Chen, Y Zhu, P Zhang, Y Zhang, X Zhu, F Ye, J Ren
IEEE Asian Solid-State Circuits Conference 2011, 349-352, 2011
9 2011 
Haozhe Zhu (朱浩哲)Fudan UniversityEmail verificata su fudan.edu.cn
