| An ultra-low-power programmable analog bionic ear processor R Sarpeshkar, C Salthouse, JJ Sit, MW Baker, SM Zhak, TKT Lu, ... IEEE Transactions on Biomedical Engineering 52 (4), 711-727, 2005 | 231 | 2005 |
| A low-power blocking-capacitor-free charge-balanced electrode-stimulator chip with less than 6 nA DC error for 1-mA full-scale stimulation JJ Sit, R Sarpeshkar IEEE Transactions on Biomedical Circuits and Systems 1 (3), 172-183, 2007 | 195 | 2007 |
| A low-power asynchronous interleaved sampling algorithm for cochlear implants that encodes envelope and phase information JJ Sit, AM Simonson, AJ Oxenham, MA Faltys, R Sarpeshkar IEEE Transactions on Biomedical Engineering 54 (1), 138-149, 2006 | 72 | 2006 |
| An analog bionic ear processor with zero-crossing detection R Sarpeshkar, MW Baker, CD Salthouse, JJ Sit, L Turicchia, SM Zhak ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 69 | 2005 |
| A micropower logarithmic A/D with offset and temperature compensation JJ Sit, R Sarpeshkar IEEE Journal of Solid-State Circuits 39 (2), 308-319, 2004 | 46 | 2004 |
| Stimulation apparatus JJ Sit, DM Pivonka US Patent 11,511,121, 2022 | 44 | 2022 |
| Devices and methods for positioning external devices in relation to implanted devices LF Hartley, C Linden, DM Pivonka, JJ Sit, LN Mishra, L Palmer, ... US Patent 11,318,315, 2022 | 28 | 2022 |
| Stimulation apparatus C Linden, A Castillo, L Palmer, JJ Sit, DM Pivonka, LN Mishra, JC Makous, ... US Patent 11,097,096, 2021 | 27 | 2021 |
| Micropower logarithmic analog to digital conversion system and method with offset and temperature compensation JJ Sit, R Sarpeshkar US Patent 7,126,509, 2006 | 27 | 2006 |
| A cochlear-implant processor for encoding music and lowering stimulation power JJ Sit, R Sarpeshkar IEEE Pervasive Computing 7 (1), 40-48, 2008 | 26 | 2008 |
| A 16-channel analog VLSI processor for bionic ears and speech-recognition front ends MW Baker, TKT Lu, CD Salthouse, JJ Sit, S Zhak, R Sarpeshkar Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003 …, 2003 | 19 | 2003 |
| A micropower analog VLSI processing channel for bionic ears and speech-recognition front ends TKT Lu, M Baker, CD Salthouse, JJ Sit, S Zhak, R Sarpeshkar 2003 IEEE International Symposium on Circuits and Systems (ISCAS) 5, V-V, 2003 | 11 | 2003 |
| Systems and methods for providing neural stimulation with an asynchronous stochastic strategy R Sarpeshkar, MA Faltys, JJ Sit US Patent 8,000,797, 2011 | 9 | 2011 |
| Stimulation apparatus C Linden, A Castillo, L Palmer, JJ Sit, DM Pivonka, LN Mishra, JC Makous, ... US Patent App. 17/379,928, 2022 | 7 | 2022 |
| Biasing techniques for subthreshold MOS resistive grids KH Wee, J Sit, R Sarpeshkar 2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2164-2167, 2005 | 7 | 2005 |
| A RF-DC Rectifier with Dual Voltage Polarity Self-Biasing for Wireless Sensor Node Application TBC Terence, V Navaneethan, LX Yang, N Utomo, L Ziming, TC Boon, ... 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 4 | 2021 |
| Stimulation apparatus JJ Sit, DM Pivonka US Patent App. 18/046,042, 2023 | 2 | 2023 |
| A low-power analog logarithmic map circuit with offset and temperature compensation for use in bionic ears JJ Sit Massachusetts Institute of Technology, 2002 | 2 | 2002 |
| An asynchronous, low-power architecture for interleaved neural stimulation, using envelope and phase information JJ Sit Massachusetts Institute of Technology, 2007 | 1 | 2007 |
| The UltraC2K: A Wire-Intensive Superscalar Processor D Henry, G Loh, R Sami, JJ Sit, V Viswanath, B Kuszmaul SRC Copper Design Challenge contest Phase-I submission, 1999 | 1 | 1999 |
