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Rob A. Rutenbar
Rob A. Rutenbar
Professor of Computer Science and Electrical and Computer Engineering, University of Pittsburgh
Verified email at pitt.edu - Homepage
Title
Cited by
Cited by
Year
Simulated annealing algorithms: An overview
RA Rutenbar
IEEE Circuits and Devices magazine 5 (1), 19-26, 1989
8301989
Computer-aided design of analog and mixed-signal integrated circuits
GGE Gielen, RA Rutenbar
Proceedings of the IEEE 88 (12), 1825-1854, 2000
7122000
OASYS: A framework for analog circuit synthesis
R Harjani, RA Rutenbar, LR Carley
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1989
5521989
Synthesis of high-performance analog circuits in ASTRX/OBLX
ES Ochotta, RA Rutenbar, LR Carley
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1996
4711996
Introduction
JM Cohn, DJ Garrod, RA Rutenbar, LR Carley
Analog Device-Level Layout Automation, 1-18, 1994
369*1994
KOAN/ANAGRAM II: New tools for device-level analog placement and routing
JM Cohn, DJ Garrod, RA Rutenbar, LR Carley
IEEE Journal of Solid-State Circuits 26 (3), 330-342, 1991
3571991
Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search
R Phelps, M Krasnicki, RA Rutenbar, LR Carley, JR Hellums
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000
3362000
Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis
BR Stanisic, NK Verghese, RA Rutenbar, LR Carley, DJ Allstot
IEEE Journal of Solid-State Circuits 29 (3), 226-238, 1994
3301994
Hierarchical modeling, optimization, and synthesis for system-level analog and RF designs
RA Rutenbar, GGE Gielen, J Roychowdhury
Proceedings of the IEEE 95 (3), 640-669, 2007
2612007
Digital circuit design challenges and opportunities in the era of nanoscale CMOS
BH Calhoun, Y Cao, X Li, K Mai, LT Pileggi, RA Rutenbar, KL Shepard
Proceedings of the IEEE 96 (2), 343-365, 2008
2422008
Reducing power by optimizing the necessary precision/range of floating-point arithmetic
JYF Tong, D Nagle, RA Rutenbar
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (3), 273-286, 2000
2222000
MAELSTROM: Efficient simulation-based synthesis for custom analog cells
M Krasnicki, R Phelps, RA Rutenbar, LR Carley
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 945-950, 1999
2041999
FPGA routing and routability estimation via Boolean satisfiability
RG Wood, RA Rutenbar
IEEE transactions on very large scale integration (VLSI) systems 6 (2), 222-231, 1998
2031998
Placement by simulated annealing on a multiprocessor
SA Kravitz, RA Rutenbar
IEEE transactions on computer-aided design of integrated circuits and …, 1987
1951987
Why quasi-Monte Carlo is better than Monte Carlo or Latin hypercube sampling for statistical circuit analysis
A Singhee, RA Rutenbar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
1892010
A comparative study of two Boolean formulations of FPGA detailed routing constraints
GJ Nam, F Aloul, KA Sakallah, RA Rutenbar
IEEE Transactions on Computers 53 (6), 688-696, 2004
1882004
Analog device-level layout automation
JM Cohn, DJ Garrod, R Carley, RA Rutenbar
Springer Science & Business Media, 1994
1751994
Statistical blockade: Very fast statistical simulation and modeling of rare circuit events and its application to memory design
A Singhee, RA Rutenbar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
1742009
Remembrance of circuits past: Macromodeling by data mining in large analog design spaces
H Liu, A Singhee, RA Rutenbar, LR Carley
Proceedings of the 39th annual Design Automation Conference, 437-442, 2002
1552002
Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application
A Singhee, RA Rutenbar
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
1452007
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