| A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface YU Jeong, H Park, C Hyun, JH Chae, SH Jeong, S Kim IEEE Journal of Solid-State Circuits 56 (4), 1278-1287, 2020 | 28 | 2020 |
| A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator JH Chae, H Ko, J Park, S Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (4), 978-982, 2019 | 25 | 2019 |
| A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation C Hyun, H Ko, JH Chae, H Park, S Kim 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2019 | 20 | 2019 |
| Duty cycle correction circuit and clock correction circuit including the same S Kim, C Joo-Hyung, DK Jeong US Patent App. 15/965,505, 2019 | 20 | 2019 |
| A 2.1-Gb/s 12-channel transmitter with phase emphasis embedded serializer for 55-in UHD intra-panel interface J Park, JH Chae, YU Jeong, JW Lee, S Kim IEEE Journal of Solid-State Circuits 53 (10), 2878-2888, 2018 | 17 | 2018 |
| A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface SK Jihwan Park, Joo-Hyung Chae, Yong-Un Jeong, Jae-Whan Lee 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 257-260, 2017 | 17* | 2017 |
| High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line M Kim, WY Shin, GM Hong, J Park, JH Chae, N Xing, JK Woo, S Kim 2013 Proceedings of the ESSCIRC (ESSCIRC), 311-314, 2013 | 16 | 2013 |
| A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner JH Chae, H Ko, J Park, S Kim IEEE Transactions on Circuits and Systems II: Express Briefs 66 (3), 372-376, 2018 | 15 | 2018 |
| A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces JH Chae, M Kim, S Choi, S Kim IEEE Transactions on Circuits and Systems II: Express Briefs 67 (2), 220-224, 2019 | 14 | 2019 |
| Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces JH Chae, YU Jeong, S Kim IEEE Transactions on Circuits and Systems I: Regular Papers 67 (9), 2972-2983, 2020 | 12 | 2020 |
| 266–2133 MHz phase shifter using all-digital delay-locked loop and triangular-modulated phase interpolator for LPDDR4X interface JH Chae, M Kim, H Ko, Y Jeong, J Park, GM Hong, DK Jeong, S Kim Electronics Letters 53 (12), 766-768, 2017 | 12 | 2017 |
| 25.1 A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation K Kim, JH Chae, J Yang, J Kang, G Lee, S Byeon, Y Kim, B Kim, DH Kim, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 344-346, 2021 | 10 | 2021 |
| A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller M Kim, JH Chae, S Choi, GM Hong, H Ko, DK Jeong, S Kim IEEE Transactions on Circuits and Systems II: Express Briefs 65 (12), 1894-1898, 2018 | 10 | 2018 |
| 0.11-2.5㎓ All-digital DLL for Mobile Memory Interface with Phase Sampling Window Adaptation to Reduce Jitter Accumulation JH Chae, M Kim, GM Hong, J Park, H Ko, WY Shin, H Chi, DK Jeong, ... JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 17 (3), 411-424, 2017 | 7 | 2017 |
| A 1.74 mW/GHz 0.11–2.5 GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers JH Chae, GM Hong, J Park, M Kim, H Ko, WY Shin, H Chi, DK Jeong, ... 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2015 | 7 | 2015 |
| A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation JH Kang, J Yang, K Kim, JH Chae, G Lee, S Byeon, B Kim, DH Kim, Y Kim, ... IEEE Journal of Solid-State Circuits 57 (1), 212-223, 2021 | 6 | 2021 |
| A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces YU Jeong, J Park, M Kim, JH Chae, J Yun, H Lee, S Kim IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1589-1593, 2020 | 6 | 2020 |
| Duty cycle detector and phase difference detector DK Jeong, S Kim, C Joo-Hyung US Patent App. 10/361,692, 2019 | 6* | 2019 |
| A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization JH Chae, M Kim, GM Hong, J Park, S Kim IEEE Access 6, 78055-78064, 2018 | 6 | 2018 |
| Multi-channel delay locked loop C Joo-Hyung, S Kim, DK Jeong US Patent 9,564,907, 2017 | 6 | 2017 |
Suhwan KimSeoul National University, Department of Electrical and Computer EngineeringGeverifieerd e-mailadres voor snu.ac.kr
