Prof. Dr. Marius Orlowski
Prof. Dr. Marius Orlowski
Virginia Tech, Bradly Department of Electrical and Computer Engineeering
Email verificata su vt.edu
Titolo
Citata da
Citata da
Anno
Charge storage structure formation in transistor with vertical channel region
MK Orlowski
US Patent 7,535,060, 2009
3552009
Charge storage structure formation in transistor with vertical channel region
MK Orlowski
US Patent 7,535,060, 2009
3552009
Carrier transport near the Si/SiO2 interface of a MOSFET
W Hnsch, T Vogelsang, R Kircher, M Orlowski
Solid-State Electronics 32 (10), 839-849, 1989
2031989
Process for forming an electrically programmable read-only memory cell
MK Orlowski, KM Chang
US Patent 5,705,415, 1998
1891998
Split-gate vertically oriented EEPROM device and process
M Orlowski, KT Chang, KE Witek, J Fitch
US Patent 6,433,382, 2002
1532002
A statistical polishing pad model for chemical-mechanical polishing
TK Yu, CC Yu, M Orlowski
Proceedings of IEEE International Electron Devices Meeting, 865-868, 1993
1321993
Semiconductor device structure and method therefor
TR White, AL Barr, BY Nguyen, MK Orlowski, MG Sadaka, VY Thean
US Patent 7,226,833, 2007
1232007
A model for phosphorus segregation at the silicon-silicon dioxide interface
F Lau, L Mader, C Mazure, C Werner, M Orlowski
Applied Physics A 49 (6), 671-675, 1989
1181989
Unified model for impurity diffusion in silicon
M Orlowski
Applied physics letters 53 (14), 1323-1325, 1988
1091988
Method of forming a transistor having multiple channels
MK Orlowski, L Mathew
US Patent 6,921,700, 2005
862005
Semiconductor structure with different lattice constant materials and method for forming the same
CL Liu, AL Barr, JM Grant, BY Nguyen, MK Orlowski, TA Stephens, ...
US Patent 6,831,350, 2004
742004
Semiconductor structure with different lattice constant materials and method for forming the same
CL Liu, AL Barr, JM Grant, BY Nguyen, MK Orlowski, TA Stephens, ...
US Patent 6,831,350, 2004
742004
Submicron short channel effects due to gate reoxidation induced lateral interstitial diffusion
M Orlowski, C Mazure, F Lau
1987 International Electron Devices Meeting, 632-635, 1987
701987
GeSOI transistor with low junction current and low junction capacitance and method for making the same
M Orlowski, S Goktepeli, CL Liu
US Patent 7,221,006, 2007
682007
Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration
MK Orlowski, VH Adams, CL Liu, MW Stoker
US Patent 7,238,580, 2007
642007
Field effect transistor having a gate dielectric with variable thickness
CA Mazure, MK Orlowski
US Patent 5,314,834, 1994
601994
Volatile resistive switching in Cu/TaOx/δ-Cu/Pt devices
T Liu, M Verma, Y Kang, M Orlowski
Applied Physics Letters 101 (7), 073510, 2012
592012
Low RC product transistors in SOI semiconductor process
AL Barr, OO Adetutu, BY Nguyen, MK Orlowski, MG Sadaka, VY Thean, ...
US Patent 7,037,795, 2006
592006
Dual surface SOI by lateral epitaxial overgrowth
BA Winstead, O Zia, MG Sadaka, MK Orlowski
US Patent 7,435,639, 2008
572008
Method of recrystallizing an amorphous region of a semiconductor
WJ Taylor Jr, M Orlowski, DC Gilmer, PV Alluri, CC Hobbs, MJ Rendon, ...
US Patent 6,573,160, 2003
542003
Il sistema al momento non pu eseguire l'operazione. Riprova pi tardi.
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