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Bikash Poudel
Bikash Poudel
Federal Reserve Bank of SF
Email verificata su sf.frb.org
Titolo
Citata da
Citata da
Anno
Design and evaluation of a reconfigurable ECU architecture for secure and dependable automotive CPS
B Poudel, A Munir
IEEE Transactions on Dependable and Secure Computing 18 (1), 235-252, 2018
332018
Design and comparative evaluation of GPGPU-and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPS
B Poudel, NK Giri, A Munir
2017 IEEE 28th International Conference on Application-specific Systems …, 2017
232017
Design and Evaluation of a Novel ECU Architecture for Secure and Dependable Automotive CPS
B Poudel, A Munir
The 13th Annual IEEE Consumer Communications & Networking Conference, 2016
92016
Design and evaluation of a PVT variation-resistant TRNG circuit
B Poudel, A Munir
2018 IEEE 36th international conference on computer design (ICCD), 514-521, 2018
72018
Evolving Side-Channel Resistant Reconfigurable Hardware for Elliptic Curve Cryptography
B Poudel, SJ Louis, A Munir
IEEE Congress on Evolutionary Computation 2017 Donostia - San Sebastián, Spain, 2017
32017
Implementation of Audio Effect Generator in FPGA
SR Chhetri, B Poudel, S Ghimire, S Shresthamali, DK Sharma
Nepal Journal of Science and Technology 15 (1), 89-98, 2014
32014
Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem
B Poudel, A Munir, J Kong, MA Khan
Journal of Low Power Electronics and Applications 11 (4), 43, 2021
2021
Multi-processor automotive electronic control unit
A Munir, B Poudel
US Patent 11,108,542, 2021
2021
Design and Evaluation of a Reliable TRNG using Probabilistic Switching Circuits
B Poudel
2017
Design and Evaluation of a Reliable TRNG Leveraging Probabilistic Switching Circuits
B Poudel
University of Nevada, Reno, 2017
2017
Algorithm for Resource-Optimized Design of any N-point FFT-Computation
P Kansakar, S Ghimire, B Poudel
Proceedings of IOE Graduate Conference, 2014, 2014
2014
Design, Simulation, Implementation, and Performance Analysis of a fixed-point 8 Point FFT Core for Real Time Application in Verilog HDL
B Poudel, M Bhattrai, S Ghimire
International Journal of Applied Research and Studies (iJARS) 3 (5), 2014
2014
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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