| A 28-GHz CMOS phased-array transceiver based on LO phase-shifting architecture with gain invariant phase tuning for 5G new radio J Pang, R Wu, Y Wang, M Dome, H Kato, H Huang, AT Narayanan, H Liu, ... IEEE Journal of Solid-State Circuits 54 (5), 1228-1242, 2019 | 175 | 2019 |
| A 28-GHz CMOS phased-array beamformer utilizing neutralized bi-directional technique supporting dual-polarized MIMO for 5G NR J Pang, Z Li, R Kubozoe, X Luo, R Wu, Y Wang, D You, AA Fadila, ... IEEE Journal of Solid-State Circuits 55 (9), 2371-2386, 2020 | 160 | 2020 |
| A 39-GHz 64-element phased-array transceiver with built-in phase and amplitude calibrations for large-array 5G NR in 65-nm CMOS Y Wang, R Wu, J Pang, D You, AA Fadila, R Saengchan, X Fu, ... IEEE Journal of Solid-State Circuits 55 (5), 1249-1269, 2020 | 158 | 2020 |
| A low-power low-noise mm-wave subsampling PLL using dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for IEEE 802.11 ad T Siriburanon, S Kondo, M Katsuragi, H Liu, K Kimura, W Deng, K Okada, ... IEEE Journal of Solid-State Circuits 51 (5), 1246-1260, 2016 | 108 | 2016 |
| A 50.1-Gb/s 60-GHz CMOS transceiver for IEEE 802.11 ay with calibration of LO feedthrough and I/Q imbalance J Pang, S Maki, S Kawai, N Nagashima, Y Seo, M Dome, H Kato, ... IEEE Journal of Solid-State Circuits 54 (5), 1375-1390, 2019 | 77 | 2019 |
| A 265- W Fractional-N Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65 … H Liu, Z Sun, H Huang, W Deng, T Siriburanon, J Pang, Y Wang, R Wu, T Someya ... IEEE Journal of Solid-State Circuits 54 (12), 3478 - 3492, 2019 | 61 | 2019 |
| An ADPLL-centric bluetooth low-energy transceiver with 2.3 mW interference-tolerant hybrid-loop receiver and 2.9 mW single-point polar transmitter in 65nm CMOS H Liu, Z Sun, D Tang, H Huang, T Kaneko, W Deng, R Wu, K Okada, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 444-446, 2018 | 61 | 2018 |
| A Sub-mW Fractional- ADPLL With FOM of −246 dB for IoT Applications H Liu, D Tang, Z Sun, W Deng, HC Ngo, K Okada IEEE Journal of Solid-State Circuits 53 (12), 3540-3552, 2018 | 57 | 2018 |
| A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of− 246dB for IoT applications in 65nm CMOS H Liu, D Tang, Z Sun, W Deng, HC Ngo, K Okada, A Matsuzawa 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 246-248, 2018 | 49 | 2018 |
| 24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802. 11ay with calibration of LO feedthrough and I/Q imbalance J Pang, S Maki, S Kawai, N Nagashima, Y Seo, M Dome, H Kato, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 424-425, 2017 | 43 | 2017 |
| A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular T Siriburanon, H Liu, K Nakata, W Deng, JH Son, DY Lee, K Okada, ... ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 39 | 2015 |
| A 39GHz 64-element phased-array CMOS transceiver with built-in calibration for large-array 5G NR Y Wang, R Wu, J Pang, D You, AA Fadila, R Saengchan, X Fu, ... 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 279-282, 2019 | 38 | 2019 |
| A DPLL-centric Bluetooth low-energy transceiver with a 2.3-mW interference-tolerant hybrid-loop receiver in 65-nm CMOS H Liu, Z Sun, D Tang, H Huang, T Kaneko, Z Chen, W Deng, R Wu, ... IEEE Journal of Solid-State Circuits 53 (12), 3672-3687, 2018 | 38 | 2018 |
| A 28GHz CMOS phased-array transceiver featuring gain invariance based on LO phase shifting architecture with 0.1-degree beam-steering resolution for 5G new radio J Pang, R Wu, Y Wang, M Dome, H Kato, H Huang, AT Narayanan, H Liu, ... 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 56-59, 2018 | 38 | 2018 |
| A 60-GHz 3.0-Gb/s spectrum efficient BPOOK transceiver for low-power short-range wireless in 65-nm CMOS Y Wang, B Liu, R Wu, H Liu, AT Narayanan, J Pang, N Li, T Yoshioka, ... IEEE Journal of Solid-State Circuits 54 (5), 1363-1374, 2019 | 37 | 2019 |
| A 28.16-Gb/s area-efficient 60-GHz CMOS bidirectional transceiver for IEEE 802.11 ay J Pang, KK Tokgoz, S Maki, Z Li, X Luo, I Abdo, S Kawai, H Liu, Z Sun, ... IEEE transactions on microwave theory and techniques 68 (1), 252-263, 2019 | 24 | 2019 |
| A 1.2 ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ... 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018 | 20 | 2018 |
| A 0.85mm2BLE Transceiver with Embedded T/R Switch, 2.6mW Fully-Passive Harmonic Suppressed Transmitter and 2.3mW Hybrid-Loop Receiver Z Sun, H Liu, D Tang, H Huang, T Kaneko, R Wu, W Deng, K Okada ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 15 | 2018 |
| A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth J Qiu, Z Sun, B Liu, W Wang, D Xu, H Herdian, H Huang, Y Zhang, ... IEEE Journal of Solid-State Circuits 56 (12), 3741-3755, 2021 | 14 | 2021 |
| A 0.4-ps-jitter− 52-dBc-spur synthesizable injection-locked PLL with self-clocked nonoverlap update and slope-balanced subsampling BBPD B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ... IEEE Solid-State Circuits Letters 2 (1), 5-8, 2019 | 13 | 2019 |
Kenichi OkadaTokyo Institute of TechnologyVerified email at ee.e.titech.ac.jp
