| Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography D Zoni, A Galimberti, W Fornaciari IEEE Access 8, 163419-163433, 2020 | 36 | 2020 |
| Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials D Zoni, A Galimberti, W Fornaciari IEEE Access 8, 75809-75821, 2020 | 36 | 2020 |
| CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs D Zoni, J Flich, W Fornaciari IEEE Transactions on Parallel and Distributed Systems, 2015 | 31 | 2015 |
| Modeling DVFS and power-gating actuators for cycle-accurate NoC-based simulators D Zoni, W Fornaciari ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (3), 1-24, 2015 | 30 | 2015 |
| Hands: Heterogeneous architectures and networks-on-chip design and simulation D Zoni, S Corbetta, W Fornaciari Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 30 | 2012 |
| MANGO: exploring manycore architectures for next-generation HPC systems J Flich, G Agosta, P Ampletzer, DA Alonso, C Brandolese, E Cappe, ... 2017 Euromicro Conference on Digital System Design (DSD), 478-485, 2017 | 29 | 2017 |
| A temperature and reliability oriented simulation framework for multi-core architectures S Corbetta, D Zoni, W Fornaciari 2012 IEEE Computer Society Annual Symposium on VLSI, 51-56, 2012 | 29 | 2012 |
| PowerTap: All-digital power meter modeling for run-time power monitoring D Zoni, L Cremona, A Cilardo, M Gagliardi, W Fornaciari Microprocessors and Microsystems 63, 128-139, 2018 | 25 | 2018 |
| A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations D Zoni, F Terraneo, W Fornaciari Journal of Signal Processing Systems, 1-15, 2015 | 25 | 2015 |
| Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems W Fornaciari, G Agosta, D Atienza, C Brandolese, L Cammoun, ... Proceedings of the 18th International Conference on Embedded Computer …, 2019 | 23 | 2019 |
| Exploring manycore architectures for next-generation HPC systems through the MANGO approach J Flich, G Agosta, P Ampletzer, DA Alonso, C Brandolese, E Cappe, ... Microprocessors and Microsystems 61, 154-170, 2018 | 23 | 2018 |
| BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers D Zoni, A Canidio, W Fornaciari, P Englezakis, C Nicopoulos, Y Sazeides Journal of Parallel and Distributed Computing 104, 130-145, 2017 | 23 | 2017 |
| An FPU design template to optimize the accuracy-efficiency-area trade-off D Zoni, A Galimberti, W Fornaciari Elsevier SUSCOM 1, 1-10, 2020 | 18 | 2020 |
| CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties K Grüttner, R Görgen, S Schreiner, F Herrera, P Peñil, J Medina, E Villar, ... Microprocessors and Microsystems 51, 39-55, 2017 | 18 | 2017 |
| A Comprehensive Side Channel Information Leakage Analysis of an In-order RISC CPU Microarchitecture D Zoni, A Barenghi, G Pelosi, W Fornaciari Transactions on Design Automation of Electronic Systems 1 (1), 26, 2018 | 17 | 2018 |
| Sensor-wise methodology to face NBTI stress of NoC buffers D Zoni, W Fornaciari 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 17 | 2013 |
| All-digital energy-constrained controller for general-purpose accelerators and cpus D Zoni, L Cremona, W Fornaciari IEEE Embedded Systems Letters 12 (1), 17-20, 2019 | 16 | 2019 |
| Darkcache: Energy-performance optimization of tiled multi-cores by adaptively power-gating llc banks D Zoni, L Colombo, W Fornaciari ACM Transactions on Architecture and Code Optimization (TACO) 15 (2), 1-26, 2018 | 16 | 2018 |
| Consolidation of multi-tier workloads with performance and reliability constraints A Sansottera, D Zoni, P Cremonesi, W Fornaciari 2012 International Conference on High Performance Computing & Simulation …, 2012 | 16 | 2012 |
| All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores D Zoni, L Cremona, W Fornaciari IEEE Transactions on Computers 69 (5), 706-721, 2020 | 15 | 2020 |
William Fornaciariprof. at Politecnico di Milano, Dipartimento di Elettronica, Informazione e BioingegneriaVerified email at polimi.it
