| A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection technique W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ... IEEE Journal of Solid-State Circuits 50 (1), 68-80, 2014 | 155 | 2014 |
| 15.1 A 0.0066mm2780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique W Deng, D Yang, T Ueno, T Siriburanon, S Kondo, K Okada, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 67 | 2014 |
| 14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique W Deng, D Yang, AT Narayanan, K Nakata, T Siriburanon, K Okada, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 61 | 2015 |
| A 1.2 ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ... 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018 | 20 | 2018 |
| A 0.4-ps-jitter− 52-dBc-spur synthesizable injection-locked PLL with self-clocked nonoverlap update and slope-balanced subsampling BBPD B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ... IEEE Solid-State Circuits Letters 2 (1), 5-8, 2019 | 13 | 2019 |
| A 0.048 mm 2 3 mW synthesizable fractional-N PLL with a soft injectionlocking technique W Deng, D Yang, AT Narayanan, K Nakata, T Siriburanon, K Okada, ... ISSCC Digest of Technical Papers 1, 2015 | 8 | 2015 |
| An LC-DCO based synthesizable injection-locked PLL with an FoM of− 250.3 dB D Yang, W Deng, B Liu, T Siriburanon, K Okada, A Matsuzawa ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 197-200, 2016 | 6 | 2016 |
| A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI AT Narayanan, W Deng, D Yang, R Wu, K Okada, A Matsuzawa 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 285-288, 2014 | 6 | 2014 |
| An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection D Yang, W Deng, AT Narayanan, K Nakata, T Siriburanon, K Okada, ... 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 1-2, 2016 | 3 | 2016 |
| A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI D Yang, W Deng, AT Narayanan, R Wu, B Liu, K Okada, A Matsuzawa IEICE Electronics Express 12 (15), 20150531-20150531, 2015 | 3 | 2015 |
| An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation D Yang, W Deng, B Liu, AT Narayanan, T Siriburanon, K Okada, ... 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 13-14, 2017 | 2 | 2017 |
| A Fully-Synthesizable 10.06 Gbps 16.1 mW Injection-Locked CDR in 28nm FDSOI AT Narayanan, W Deng, D Yang, R Wu, K Okada, A Matsuzawa IEICE Transactions on Electronics 100 (3), 259-267, 2017 | 1 | 2017 |
| A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI D Yang, T Ueno, W Deng, Y Terashima, K Nakata, AT Narayanan, R Wu, ... IEICE Transactions on Electronics 99 (6), 632-640, 2016 | 1 | 2016 |
| An HDL-synthesized gated-edge-injection PLL with a current output DAC D Yang, W Deng, T Ueno, T Siriburanon, S Kondo, K Okada, ... The 20th Asia and South Pacific Design Automation Conference, 2-3, 2015 | 1 | 2015 |
| A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11 ad Compliant 60GHz Transmitter in 65nm CMOS B Liu, Y Wang, J Pang, H Zhang, D Yang, AT Narayanan, DY Lee, ... IEICE Transactions on Electronics 101 (2), 126-134, 2018 | | 2018 |
| A Study of Synthesizable Phase-Locked Loop for Clock Generation D Yang (No Title), 2017 | | 2017 |
Kenichi OkadaTokyo Institute of TechnologyVerified email at ee.e.titech.ac.jp
