Baris Taskin
Baris Taskin
Professor of ECE, Drexel University
Email verificata su coe.drexel.edu - Home page
Titolo
Citata da
Citata da
Anno
Timing optimization through clock skew scheduling
IS Kourtev, B Taskin, EG Friedman
Springer Science & Business Media, 2008
1072008
Improving line-based QCA memory cell design through dual phase clocking
B Taskin, B Hong
IEEE transactions on very large scale integration (VLSI) systems 16 (12 …, 2008
512008
Delay insertion method in clock skew scheduling
B Taskin, IS Kourtev
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
442006
Timing-driven physical design for VLSI circuits using resonant rotary clocking
B Taskin, J Wood, IS Kourtev
2006 49th IEEE International Midwest Symposium on Circuits and Systems 1 …, 2006
262006
Design methodology for voltage-scaled clock distribution networks
C Sitik, W Liu, B Taskin, E Salman
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (10 …, 2016
242016
Synchrotrace: Synchronization-aware architecture-agnostic traces for light-weight multicore simulation
S Nilakantan, K Sangaiah, A More, G Salvadory, B Taskin, M Hempstead
2015 IEEE International Symposium on Performance Analysis of Systems and …, 2015
212015
FinFET-based low-swing clocking
C Sitik, E Salman, L Filippini, SJ Yoon, B Taskin
ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (2), 1-20, 2015
202015
A shift-register-based QCA memory architecture
B Taskin, A Chiu, J Salkind, D Venutolo
ACM Journal on Emerging Technologies in Computing Systems (JETC) 5 (1), 1-18, 2009
182009
CROA: Design and analysis of the custom rotary oscillatory array
V Honkote, B Taskin
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (10 …, 2010
172010
Custom topology rotary clock router with tree subnetworks
B Taskin, J Demaio, O Farell, M Hazeltine, R Ketner
ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (3 …, 2009
162009
Dual-phase line-based QCA memory design
B Taskin, B Hong
2006 Sixth IEEE Conference on Nanotechnology 1, 302-305, 2006
162006
Innovative propagation mechanism for inter-chip and intra-chip communication
Y Liu, V Pano, D Patron, K Dandekar, B Taskin
2015 IEEE 16th Annual Wireless and Microwave Technology Conference (WAMICON …, 2015
152015
Clock mesh synthesis with gated local trees and activity driven register clustering
J Lu, X Mao, B Taskin
2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 691-697, 2012
152012
Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC
A More, B Taskin
23rd IEEE International SOC Conference, 447-452, 2010
152010
Clock buffer polarity assignment considering capacitive load
J Lu, B Taskin
2010 11th International Symposium on Quality Electronic Design (ISQED), 765-770, 2010
152010
Custom rotary clock router
V Honkote, B Taskin
2008 IEEE International Conference on Computer Design, 114-119, 2008
152008
Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits
B Taskin, IS Kourtev
IEEE transactions on very large scale integration (VLSI) systems 12 (1), 12-27, 2004
152004
Integrated clock mesh synthesis with incremental register placement
J Lu, X Mao, B Taskin
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
142012
A reconfigurable clock polarity assignment flow for clock gated designs
J Lu, Y Teng, B Taskin
IEEE transactions on very large scale integration (VLSI) systems 20 (6 …, 2011
142011
Steiner tree based rotary clock routing with bounded skew and capacitive load balancing
J Lu, V Honkote, X Chen, B Taskin
2011 Design, Automation & Test in Europe, 1-6, 2011
142011
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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