Krste Asanovic

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David PattersonProfessor of Computer Science, UC BerkeleyEmail verificata su cs.berkeley.edu
Yunsup LeeSiFiveEmail verificata su sifive.com
Andrew WatermanUC BerkeleyEmail verificata su eecs.berkeley.edu
John WAWRZYNEKProfessor of EECS, University of California, BerkeleyEmail verificata su berkeley.edu
Borivoje NikolicUniversity of California BerkeleyEmail verificata su berkeley.edu
Christopher BattenCornell UniversityEmail verificata su cornell.edu
Vladimir StojanovicProfessor of Electrical Engineering and Computer Sciences, University of CaliforniaEmail verificata su berkeley.edu
John KubiatowiczUniversity of California at BerkeleyEmail verificata su cs.berkeley.edu
Scott BeamerUC Santa CruzEmail verificata su ucsc.edu
Jonathan Bachrachadjunct assistant professor of computer science, uc berkeley universityEmail verificata su eecs.berkeley.edu
Katherine YelickAssociate Laboratory Director of Computing Sciences, LBNL and EECS Professor, UC BerkeleyEmail verificata su lbl.gov
Nelson MorganICSIEmail verificata su icsi.berkeley.edu
Henry CookGraduate Student, EECS Department, University of California BerkeleyEmail verificata su eecs.berkeley.edu
James W DEMMELProfessor of EECS and Mathematics, UC BerkeleyEmail verificata su berkeley.edu
Emmett WitchelProfessor of Computer Science, The University of Texas at AustinEmail verificata su cs.utexas.edu
Brian ZimmerSenior Research Scientist, NVIDIAEmail verificata su nvidia.com
Martin MaasGoogle BrainEmail verificata su google.com
John ShalfDepartment Head for Computer Science, Lawrence Berkeley National LaboratoryEmail verificata su lbl.gov
Christos KozyrakisStanford UniversityEmail verificata su stanford.edu
Jeffrey A. BilmesProfessor of Electrical Engineering and Computer Science, University of Washington SeattleEmail verificata su uw.edu

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Krste Asanovic

UC Berkeley

Email verificata su berkeley.edu - Home page

Computer Architecture VLSI Design Parallel Programming


Titolo Ordina per citazioni Ordina per anno Ordina per titolo	Citata da Citata da	Anno
The landscape of parallel computing research: A view from berkeley K Asanovic, R Bodik, BC Catanzaro, JJ Gebis, P Husbands, K Keutzer, ... eScholarship, University of California 1, 1, 2006	3068	2006
Single-chip microprocessor that communicates directly using light C Sun, MT Wade, Y Lee, JS Orcutt, L Alloatti, MS Georgas, AS Waterman, ... Nature 528 (7583), 534-538, 2015	1179	2015
Chisel: constructing hardware in a scala embedded language J Bachrach, H Vo, B Richards, Y Lee, A Waterman, R Avižienis, ... Proceedings of the 49th Annual Design Automation Conference, 1216-1225, 2012	987	2012
A view of the parallel computing landscape K Asanovic, R Bodik, J Demmel, T Keaveny, K Keutzer, J Kubiatowicz, ... Communications of the ACM 52 (10), 56-67, 2009	923	2009
Optimizing matrix multiply using PHiPAC: a portable, high-performance, ANSI C coding methodology J Bilmes, K Asanovic, CW Chin, J Demmel ACM International Conference on Supercomputing 25th Anniversary Volume, 253-260, 1997	787	1997
Unbounded transactional memory CS Ananian, K Asanovic, BC Kuszmaul, CE Leiserson, S Lie 11th International Symposium on High-Performance Computer Architecture, 316-327, 2005	744	2005
Energy-aware lossless data compression KC Barr, K Asanović ACM Transactions on Computer Systems (TOCS) 24 (3), 250-291, 2006	693	2006
The Rocket Chip Generator K Asanovi, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... Technical Report No. UCB/EECS-2016-17, 2016	684*	2016
Direction-optimizing breadth-first search S Beamer, K Asanovic, D Patterson SC'12: Proceedings of the International Conference on High Performance …, 2012	667	2012
Building many-core processor-to-DRAM networks with monolithic CMOS silicon photonics C Batten, A Joshi, J Orcutt, A Khilo, B Moss, CW Holzwarth, MA Popovic, ... IEEE Micro 29 (4), 8-21, 2009	568	2009
The RISC-V instruction set manual: User-level ISA version 2.0 A Waterman, Y Lee, DA Patterson, K Asanovic Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley, Berkeley, CA …, 2014	508*	2014
Victim replication: Maximizing capacity while hiding wire delay in tiled chip multiprocessors M Zhang, K Asanovic 32nd International Symposium on Computer Architecture (ISCA'05), 336-345, 2005	501	2005
Reducing power density through activity migration S Heo, K Barr, K Asanović Proceedings of the 2003 international symposium on Low power electronics and …, 2003	450	2003
Silicon-photonic clos networks for global on-chip communication A Joshi, C Batten, YJ Kwon, S Beamer, I Shamim, K Asanovic, ... 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 124-133, 2009	434	2009
Mondrian memory protection E Witchel, J Cates, K Asanovic Proceedings of the 10th Int’l Conference on Architectural Support for …, 2002	432	2002
Keystone: An open framework for architecting trusted execution environments D Lee, D Kohlbrenner, S Shinde, K Asanović, D Song Proceedings of the Fifteenth European Conference on Computer Systems, 1-16, 2020	374*	2020
The GAP benchmark suite S Beamer, K Asanović, D Patterson arXiv preprint arXiv:1508.03619, 2015	358	2015
Dynamic zero compression for cache energy reduction L Villa, M Zhang, K Asanović MICRO 33: Proceedings of the 33rd annual international symposium on Microar …, 2000	289	2000
Phantom: Practical oblivious computation in a secure processor M Maas, E Love, E Stefanov, M Tiwari, E Shi, K Asanovic, J Kubiatowicz, ... Proceedings of the 2013 ACM SIGSAC conference on Computer & communications …, 2013	282	2013
Scalable processors in the billion-transistor era: IRAM CE Kozyrakis, S Perissakis, D Patterson, T Anderson, K Asanovic, ... IEEE Computer Special Issue: Future Microprocessors-How to use a Billion …, 1997	279	1997

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