| A 28-GHz CMOS phased-array beamformer utilizing neutralized bi-directional technique supporting dual-polarized MIMO for 5G NR J Pang, Z Li, R Kubozoe, X Luo, R Wu, Y Wang, D You, AA Fadila, ... IEEE Journal of Solid-State Circuits 55 (9), 2371-2386, 2020 | 160 | 2020 |
| A 39-GHz 64-element phased-array transceiver with built-in phase and amplitude calibrations for large-array 5G NR in 65-nm CMOS Y Wang, R Wu, J Pang, D You, AA Fadila, R Saengchan, X Fu, ... IEEE Journal of Solid-State Circuits 55 (5), 1249-1269, 2020 | 158 | 2020 |
| A 39GHz 64-element phased-array CMOS transceiver with built-in calibration for large-array 5G NR Y Wang, R Wu, J Pang, D You, AA Fadila, R Saengchan, X Fu, ... 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 279-282, 2019 | 38 | 2019 |
| A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration B Liu, Y Zhang, J Qiu, HC Ngo, W Deng, K Nakata, T Yoshioka, J Emmei, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 603-616, 2020 | 33 | 2020 |
| A fully-synthesizable fractional-N injection-locked PLL for digital clocking with triangle/sawtooth spread-spectrum modulation capability in 5-nm CMOS B Liu, Y Zhang, J Qiu, H Huang, Z Sun, D Xu, H Zhang, Y Wang, J Pang, ... IEEE Solid-State Circuits Letters 3, 34-37, 2020 | 23 | 2020 |
| A 1.2 ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ... 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018 | 20 | 2018 |
| An HDL-described fully-synthesizable sub-GHz IoT transceiver with ring oscillator based frequency synthesizer and digital background EVM calibration B Liu, Y Zhang, J Qiu, W Deng, Z Xu, H Zhang, J Pang, Y Wang, R Wu, ... 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019 | 15 | 2019 |
| A 32kHz-Reference 2.4 GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth J Qiu, Z Sun, B Liu, W Wang, D Xu, H Herdian, H Huang, Y Zhang, ... IEEE Journal of Solid-State Circuits 56 (12), 3741-3755, 2021 | 14 | 2021 |
| A 0.4-ps-jitter− 52-dBc-spur synthesizable injection-locked PLL with self-clocked nonoverlap update and slope-balanced subsampling BBPD B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ... IEEE Solid-State Circuits Letters 2 (1), 5-8, 2019 | 13 | 2019 |
| A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal Y Wang, D You, X Fu, T Nakamura, AA Fadila, T Someya, A Kawaguchi, ... IEEE Journal of Solid-State Circuits 57 (2), 356-370, 2021 | 12 | 2021 |
| A CMOS 24–30-GHz low-phase-variation variable gain amplifier design for 5G new radio J Qiu, J Pang, B Liu, X Luo, Y Wang, Y Zhang, A Shirane, K Okada IEEE Solid-State Circuits Letters 5, 146-149, 2022 | 5 | 2022 |
| A 29% PAE 1.5 Bit-DSM-based polar transmitter with spur-mitigated injection-locked PLL Y Zhang, B Liu, X Gu, C Wang, K Yanagisawa, J Qiu, Y Wang, J Pang, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 5 | 2020 |
| A 6.5-to-8GHz cascaded dual-fractional-N digital PLL achieving-63.7 dBc fractional spurs with 50MHz reference D Xu, Y Zhang, H Huang, Z Sun, B Liu, AA Fadila, J Qiu, Z Liu, W Wang, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 4 | 2023 |
| A 1-bit-DSM-based digital polar power amplifier supporting 1024-QAM Y Zhang, B Liu, J Qiu, A Shirane, K Okada IEEE Solid-State Circuits Letters 5, 130-133, 2022 | 3 | 2022 |
| 4.4 A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration J Qiu, W Wang, Z Sun, B Liu, Y Zhang, D Xu, H Huang, AF Aviat, Z Liu, ... 2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023 | 2 | 2023 |
| A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter Y Zhang, Z Sun, B Liu, J Qiu, D Xu, Y Zhang, X Fu, D You, H Huang, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 1 | 2023 |
| A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components Y Zhang, B Liu, T Someya, R Wu, J Qiu, A Shirane, K Okada IEICE Transactions on Electronics 105 (7), 334-342, 2022 | 1 | 2022 |
| 10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1 dBc Fractional Spur and 143.7 fs Integrated Jitter D Xu, Z Liu, Y Kuai, H Huang, Y Zhang, Z Sun, B Liu, W Wang, Y Xiong, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 192-194, 2024 | | 2024 |
| A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range H Huáng, B Liu, Z Liu, D Xu, Y Zhang, W Madany, J Qiu, Z Sun, AA Fadila, ... IEEE Solid-State Circuits Letters, 2024 | | 2024 |
| A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta–Sigma Modulator and Hybrid FIR Filter Y Zhang, Z Sun, B Liu, J Qiu, D Xu, Y Zhang, X Fu, D You, H Huang, ... IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
