ashwini nanda
ashwini nanda
Founder and CEO, HPC Links
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Cited by
Cited by
Measurement, analysis and performance improvement of the Apache web server
Y Hu, A Nanda, Q Yang
1999 IEEE International Performance, Computing and Communications Conference …, 1999
Energy optimization of multilevel cache architectures for RISC and CISC processors
U Ko, PT Balsara, AK Nanda
IEEE transactions on very large scale integration (VLSI) systems 6 (2), 299-308, 1998
Pipelined microprocessor with branch misprediction cache circuits, systems and methods
JO Bondi, S Dutta, AK Nanda
US Patent 5,881,277, 1999
Coherence controller architectures for SMP-based CC-NUMA multiprocessors
MM Michael, AK Nanda, BH Lim, ML Scott
Proceedings of the 24th Annual International Symposium on Computer …, 1997
MemorIES3: a programmable, real-time hardware emulation tool for multiprocessor server design
A Nanda, KK Mak, K Sugarvanam, RK Sahoo, V Soundarararjan, ...
ACM SIGARCH Computer Architecture News 28 (5), 37-48, 2000
Energy optimization of multi-level processor cache architectures
U Ko, PT Balsara, AK Nanda
Proceedings of the 1995 international symposium on Low power design, 45-49, 1995
Two level virtual channels
DJ Joseph, MM Michael, A Nanda
US Patent 6,628,615, 2003
Scheduling directed task graphs on multiprocessors using simulated annealing
AK Nanda, D DeGroot, DL Stenger
1992 12th International Conference on Distributed Computing System, 20, 21 …, 1992
Design and performance of directory caches for scalable shared memory multiprocessors
MM Michael, AK Nanda
Proceedings Fifth International Symposium on High-Performance Computer …, 1999
High-throughput coherence controllers
AK Nanda, AT Nguyen, MM Michael, DJ Joseph
Proceedings Sixth International Symposium on High-Performance Computer …, 2000
Accuracy and speed-up of parallel trace-driven architectural simulation
AT Nguyen, P Bose, K Ekanadham, A Nanda, M Michael
Proceedings 11th International Parallel Processing Symposium, 39-44, 1997
State-based allocation and replacement for improved hit ratio in directory caches
MM Michael, A Nanda, TB Smith III
US Patent 6,826,651, 2004
Cell/BE blades: Building blocks for scalable, real-time, interactive, and digital media servers
AK Nanda, JR Moulic, RE Hanson, G Goldrian, MN Day, BD D'Amora, ...
IBM Journal of Research and Development 51 (5), 573-582, 2007
Performance of multistage bus networks for a distributed shared memory multiprocessor
LN Bhuyan, RR Iyer, T Askar, AK Nanda, M Kumar
IEEE Transactions on Parallel and Distributed Systems 8 (1), 82-95, 1997
Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache
AK Nanda, JH Shiell
US Patent 6,038,645, 2000
Design and analysis of cache coherent multistage interconnection networks
AK Nanda, LN Bhuyan
IEEE Transactions on Computers 42 (4), 458-470, 1993
Plug-in accelerator
BD D'amora, JR Moulic, AK Nanda
US Patent 8,838,674, 2014
The misprediction recovery cache
AK Nanda, JO Bondi, S Dutta
International journal of parallel programming 26 (4), 383-415, 1998
Complete and concise remote (CCR) directory
DJ Joseph, MM Michael, A Nanda
US Patent 6,338,123, 2002
Using switch directories to speed up cache-to-cache transfers in CC-NUMA multiprocessors
R Iyer, LN Bhuyan, A Nanda
Proceedings 14th International Parallel and Distributed Processing Symposium …, 2000
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