vinay saripalli
vinay saripalli
PhD in computer Science and Engineering, Penn State University
Verified email at
Cited by
Cited by
IEEE International Electron Devices Meeting (IEDM)
CH Jan, M Agostinelli, M Buehler, ZP Chen, SJ Choi, G Curello, ...
San Francisco, USA, 3.1, 2012
Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design
V Saripalli, S Datta, V Narayanan, JP Kulkarni
2011 IEEE/ACM International Symposium on Nanoscale Architectures, 45-52, 2011
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores
V Saripalli, A Mishra, S Datta, V Narayanan
Proceedings of the 48th Design Automation Conference, 729-734, 2011
Exploiting heterogeneity for energy efficiency in chip multiprocessors
V Saripalli, G Sun, A Mishra, Y Xie, S Datta, V Narayanan
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1 (2 …, 2011
Steep-slope devices: From dark to dim silicon
K Swaminathan, E Kultursay, V Saripalli, V Narayanan, MT Kandemir, ...
IEEE Micro 33 (5), 50-59, 2013
Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores
K Swaminathan, E Kultursay, V Saripalli, V Narayanan, M Kandemir, ...
IEEE/ACM International Symposium on Low Power Electronics and Design, 247-252, 2011
Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores
E Kultursay, K Swaminathan, V Saripalli, V Narayanan, MT Kandemir, ...
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware …, 2012
Ultra low power circuit design using tunnel FETs
R Mukundrajan, M Cotter, V Saripalli, MJ Irwin, S Datta, V Narayanan
2012 IEEE Computer Society Annual Symposium on VLSI, 153-158, 2012
Reconfigurable BDD based quantum circuits
S Eachempati, V Saripalli, N Vijaykrishnan, S Datta
2008 IEEE International Symposium on Nanoscale Architectures, 61-67, 2008
Exploration of vertical MOSFET and tunnel FET device architecture for sub 10nm node applications
H Liu, DK Mohata, A Nidhi, V Saripalli, V Narayanan, S Datta
70th Device Research Conference, 233-234, 2012
Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistor
DK Mohata, R Bijesh, V Saripalli, T Mayer, S Datta
69th Device Research Conference, 203-204, 2011
Energy-delay performance of nanoscale transistors exhibiting single electron behavior and associated logic circuits
V Saripalli, L Liu, S Datta, V Narayanan
Journal of Low Power Electronics 6 (3), 415-428, 2010
III-V Tunnel FET Model 1.0. 0
H Liu, V Saripalli, V Narayanan, S Datta
Retrieved April 18, 2016, 2014
Iii-v tunnel fet model
H Liu, V Saripalli, V Narayanan, S Datta
nanoHUB, 2015
Asymmetric tunnel field-effect transistors as frequency multipliers
H Madan, V Saripalli, H Liu, S Datta
IEEE electron device letters 33 (11), 1547-1549, 2012
Device circuit co-design using classical and non-classical III–V Multi-Gate Quantum-Well FETs (MuQFETs)
L Liu, V Saripalli, V Narayanan, S Datta
2011 International Electron Devices Meeting, 4.5. 1-4.5. 4, 2011
Impact of single trap random telegraph noise on heterojunction TFET SRAM stability
R Pandey, V Saripalli, JP Kulkarni, V Narayanan, S Datta
IEEE Electron Device Letters 35 (3), 393-395, 2014
Low Power Loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As Tunnel FETs
V Saripalli, DK Mohata, S Mookerjea, S Datta, V Narayanan
68th Device Research Conference, 101-102, 2010
Design of energy-efficient circuits and systems using tunnel field effect transistors
R Mukundrajan, M Cotter, S Bae, V Saripalli, MJ Irwin, S Datta, ...
IET Circuits, Devices & Systems 7 (5), 294-303, 2013
TFET based 4T memory devices
V Saripalli, D Mohata, S Mookherjea, S Datta, V Narayanan
US Patent 8,638,591, 2014
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