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Gaurav kaushal
Gaurav kaushal
Verified email at iiitm.ac.in
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Cited by
Cited by
Year
Vertical silicon nanowire gate-all-around field effect transistor based nanoscale CMOS
S Maheshwaram, SK Manhas, G Kaushal, B Anand, N Singh
IEEE electron device letters 32 (8), 1011-1013, 2011
412011
A degradation model of double gate and gate-all-around MOSFETs with interface trapped charges including effects of channel mobile charge carriers
R Shankar, G Kaushal, S Maheshwaram, S Dasgupta, SK Manhas
IEEE Transactions on Device and Materials Reliability 14 (2), 689-697, 2014
272014
Vertical nanowire CMOS parasitic modeling and its performance analysis
S Maheshwaram, SK Manhas, G Kaushal, B Anand, N Singh
IEEE transactions on electron devices 60 (9), 2943-2950, 2013
242013
Radiation effects in Si-NW GAA FET and CMOS inverter: A TCAD simulation study
G Kaushal, SS Rathod, S Maheshwaram, SK Manhas, AK Saxena, ...
IEEE transactions on electron devices 59 (5), 1563-1566, 2012
192012
Impact of series resistance on Si nanowire MOSFET performance
G Kaushal, SK Manhas, S Maheshwaram, S Dasgupta
Journal of Computational Electronics 12 (2), 306-315, 2013
172013
Device circuit co-design issues in vertical nanowire CMOS platform
S Maheshwaram, SK Manhas, G Kaushal, B Anand, N Singh
IEEE Electron Device Letters 33 (7), 934-936, 2012
162012
Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs
G Kaushal, K Subramanyam, SN Rao, G Vidya, R Ramya, S Shaik, ...
2014 International SoC Design Conference (ISOCC), 32-33, 2014
92014
Double node upset tolerant RHBD15T SRAM cell design for space applications
CHN Raghuram, B Gupta, G Kaushal
IEEE Transactions on Device and Materials Reliability 20 (1), 181-190, 2020
82020
Novel Design Methodology Using Sizing in Nanowire CMOS Logic
G Kaushal, SK Manhas, S Maheshwaram, B Anand, S Dasgupta, N Singh
IEEE Transactions on Nanotechnology 13 (4), 650-658, 2014
82014
Single-event multiple effect tolerant RHBD14T SRAM cell design for space applications
NR CH, B Gupta, G Kaushal
IEEE Transactions on Device and Materials Reliability 21 (1), 48-56, 2021
72021
Semantic image completion and enhancement using deep learning
V Chandak, P Saxena, M Pattanaik, G Kaushal
2019 10th International Conference on Computing, Communication and …, 2019
72019
Low power SRAM design for 14 nm GAA Si-nanowire technology
G Kaushal, H Jeong, S Maheshwaram, SK Manhas, S Dasgupta, SO Jung
Microelectronics Journal 46 (12), 1239-1247, 2015
62015
Electron transport in C3N monolayer: DFT analysis of volatile organic compound sensing
S Agrawal, G Kaushal, A Srivastava
Chemical Physics Letters 762, 138121, 2021
52021
Three dimensional route planning for multiple unmanned aerial vehicles using salp swarm algorithm
P Saxena, S Tayal, R Gupta, A Maheshwari, G Kaushal, R Tiwari
arXiv preprint arXiv:1911.10519, 2019
42019
Tuning source/drain extension profile for current matching in nanowire CMOS logic
G Kaushal, SK Manhas, S Maheshwaram, S Dasgupta, B Anand, N Singh
IEEE transactions on nanotechnology 11 (5), 1033-1039, 2012
32012
A low power low noise analog front-end for ECG recording
S Dey, M Pattanaik, G Kaushal
Analog Integrated Circuits and Signal Processing 109 (2), 449-458, 2021
22021
N-Doped Zigzag Graphene Nanoribbons For Nanoscale Interconnects
S Agrawal, A Srivastava, G Kaushal
2020 IEEE 10th International Conference Nanomaterials: Applications …, 2020
22020
Robust SRAM cell development for single-event multiple effects
NR CH, D Manohar Reddy, P Kishore Kumar, G Kaushal
International Symposium on VLSI Design and Test, 335-347, 2018
22018
A high performance vertical Si nanowire CMOS for ultra high density circuits
S Maheshwaram, G Kaushal, SK Manhas
2010 IEEE Asia Pacific Conference on Circuits and Systems, 1219-1222, 2010
22010
Modeling of interface trap charges induced degradation in underlap DG and GAA MOSFETs
S Agrawal, A Srivastava, G Kaushal
Microelectronics Reliability 125, 114344, 2021
12021
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