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Dr. Aditya Japa
Dr. Aditya Japa
Assistant Professor, koneru lakshmaiah education foundation hyderabad
Verified email at klh.edu.in
Title
Cited by
Cited by
Year
Reliability Enhancement of a Steep Slope Tunnel Transistor based Ring Oscillator Designs with Circuit Interaction
RV Aditya J, Harshita V
IET Circuits, Devices & Systems, 8, 2016
18*2016
Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm
H Vallabhaneni., A Japa., S Sadulla, KS Rama, V Ramesh
Devices, Circuits and Systems (ICDCS), 2014 2nd International Conference on, 1-5, 2014
182014
Hardware security exploiting post-CMOS devices: fundamental device characteristics, state-of-the-art countermeasures, challenges and roadmap
A Japa, MK Majumder, SK Sahoo, R Vaddi, BK Kaushik
IEEE Circuits and Systems Magazine 21 (3), 4-30, 2021
152021
Negative capacitance FETs for energy efficient and hardware secure logic designs
RC Bheemana, A Japa, SS Yellampalli, R Vaddi
Microelectronics Journal 119, 105320, 2022
132022
Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design
RC Bheemana, A Japa, S sankar Yellampalli, R Vaddi
Microelectronics Journal 133, 105711, 2023
102023
Introduction to microelectronics to nanoelectronics: design and technology
MK Majumder, VR Kumbhare, A Japa, BK Kaushik
CRC Press, 2020
92020
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities
RV Aditya Japa , T. Nagateja, Santosh Kumar Vishvakarma, Palagani Yellappa ...
IEEE International Symposium on Circuits and Systems (ISCAS), 2018, 2018
92018
Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks
A Japa, MK Majumder, SK Sahoo, R Vaddi
IET Circuits, Devices & Systems 13 (5), 689-695, 2019
72019
Steep switching NCFET based logic for future energy efficient electronics
RC Bheemana, A Japa, S Yellampalli, R Vaddi
2021 IEEE International Symposium on Smart Electronic Systems (iSES), 327-330, 2021
52021
Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator
A Japa, M Kumar Majumder, SK Sahoo, R Vaddi
IET Circuits, Devices & Systems 14 (5), 640-647, 2020
52020
Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage
A Japa, MK Majumder, SK Sahoo, R Vaddi
Journal of Circuit Theory and Applications, Wiely, 2020
52020
Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption
A Japa, SK Sahoo, R Vaddi, MK Majumder
Journal of Computational Electronics 22 (1), 178-189, 2023
32023
Tunneling field effect transistors for energy efficient logic, sensor interface and 3D IC circuits for IoT platforms
J Aditya, T Nagateja, R Vaddi
2017 IEEE International Symposium on Nanoelectronic and Information Systems …, 2017
32017
Exploiting the steep subthreshold slope characteristics of tunnel transistors for wide tuning range voltage controlled ring oscillator (VCRO) design at scaled supply voltages …
J Aditya, S Sadulla, R Vaddi
2016 3rd International Conference on Emerging Electronics (ICEE), 1-2, 2016
32016
Design and security evaluation of negative capacitance FETs for energy efficient and DPA attack resilient PRSENT-80 block cipher design at scaled VDD
RC Bheemana, PK Rao, A Japa, SS Yellampalli, R Vaddi
27th International Conference on Advanced Computing and Communications …, 2023
12023
Exploiting characteristics of steep slope tunnel transistors towards energy efficient and reliable buffer designs for IoT SoCs
J Aditya, V Harshita, R Vaddi
VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee …, 2017
12017
Tunnel FET based Energy Efficient Circuit Design with Enhanced Hardware Security
J Aditya
Raipur, 2023
2023
Processor based Intrinsic PUF Design for Approximate Computing: Faith or Reality?
A Japa, J Zhang, W Liu, C Gu
2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 1-6, 2023
2023
A Reconfigurable Arbiter PUF Based on VGSOT MTJ
KK Das, A Japa, D Gupta
International Symposium on VLSI Design and Test, 320-330, 2022
2022
Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things
J Aditya, M Manoj Kumar, S Subhendu K., V Ramesh
Journal of Circuit Theory and Applications, Wiely, 2021
2021
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