Peter Debacker
Peter Debacker
Program Manager, imec
Verified email at
Cited by
Cited by
Dynamic time-slot allocation for QoS enabled networks on chip
T Marescaux, B Bricke, P Debacker, V Nollet, H Corporaal
3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005., 47-52, 2005
Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI
G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ...
IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018
Extreme scaling enabled by 5 tracks cells: holistic design-device co-optimization for FinFETs and lateral nanowires
M Garcia Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, ...
IEEE International Electron Devices Meeting-IEDM, 687-690, 2016
Standard cell design in N7: EUV vs. immersion
B Chava, D Rio, Y Sherazi, D Trivkovic, W Gillijns, P Debacker, ...
Design-Process-Technology Co-optimization for Manufacturability IX 9427, 94270E, 2015
Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology node
C Pan, P Raghavan, D Yakimets, P Debacker, F Catthoor, N Collaert, ...
IEEE Transactions on Electron Devices 62 (10), 3125-3132, 2015
The impact of sequential-3D integration on semiconductor scaling roadmap
A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017
Low track height standard cell design in iN7 using scaling boosters
SMY Sherazi, C Jha, D Rodopoulos, P Debacker, B Chava, L Matti, ...
Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017
An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11 AD standard
M Li, F Naessens, P Debacker, P Raghavan, C Desset, M Li, A Dejonghe, ...
SiPS 2013 Proceedings, 112-117, 2013
Architectural strategies in standard-cell design for the 7 nm and beyond technology node
SMY Sherazi, B Chava, P Debacker, MG Bardon, P Schuddinck, F Firouzi, ...
Journal of Micro/Nanolithography, MEMS, and MOEMS 15 (1), 013507, 2016
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs
BW Ku, P Debacker, D Milojevic, P Raghavan, D Verkest, A Thean, ...
Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016
Design-technology co-optimization for OxRRAM-based synaptic processing unit
A Mallik, D Garbin, A Fantini, D Rodopoulos, R Degraeve, J Stuijt, AK Das, ...
2017 Symposium on VLSI Technology, T178-T179, 2017
An energy efficient 18Gbps LDPC decoding processor for 802.11 ad in 28nm CMOS
M Li, JW Weijers, V Derudder, I Vos, M Rykunov, S Dupont, P Debacker, ...
2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-5, 2015
Embedded ranging system in ISM band
X Yin, J Bauwelinck, G Torfs, P Demuytere, J Vandewege, H Tubbax, ...
Electronics Letters 44 (17), 1043-1045, 2008
Design and pitch scaling for affordable node transition and EUV insertion scenario
R Kim, J Ryckaert, P Raghavan, Y Sherazi, P Debacker, D Trivkovic, ...
Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017
On-chip interconnect trends, challenges and solutions: how to keep RC and reliability under control
Z Tőkei, I Ciofi, P Roussel, P Debacker, P Raghavan, MH Van Der Veen, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
Integrated circuit power distribution network
P Debacker, P Raghavan, VC Gerousis
US Patent 10,510,774, 2019
The defect-centric perspective of device and circuit reliability—from gate oxide defects to circuits
B Kaczer, J Franco, P Weckx, PJ Roussel, M Simicic, V Putcha, E Bury, ...
Solid-State Electronics 125, 52-62, 2016
Computation-skip error mitigation scheme for power supply voltage scaling in recursive applications
Y Huang, M Li, C Li, P Debacker, L Van der Perre
Journal of Signal Processing Systems 84 (3), 413-424, 2016
Capturing true workload dependency of BTI-induced degradation in CPU components
D Stamoulis, S Corbetta, D Rodopoulos, P Weckx, P Debacker, BH Meyer, ...
2016 International Great Lakes Symposium on VLSI (GLSVLSI), 373-376, 2016
Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet
SMY Sherazi, M Cupak, P Weckx, O Zografos, D Jang, P Debacker, ...
Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019
The system can't perform the operation now. Try again later.
Articles 1–20