Jaeduk Han
Jaeduk Han
Hanyang University
Geverifieerd e-mailadres voor eecs.berkeley.edu - Homepage
TitelGeciteerd doorJaar
Cable connector retaining assembly, system, and method of assembling same
MG Clark, RC Laning, CM Marroquin, BJ Stanczyk, RV Tointon
US Patent 6,964,578, 2005
452005
A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET
J Im, D Freitas, A Bantug Roldan, R Casey, S Chen, CH Adam Chou, ...
IEEE Journal of Solid-State Circuits 52 (12), 3486-3502, 2017
402017
6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET
J Im, D Freitas, A Bantug Roldan, R Casey, S Chen, CH Adam Chou, ...
Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 114-115, 2017
40*2017
A 4.8 Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface
WY Shin, GM Hong, H Lee, JD Han, S Kim, KS Park, DH Lim, JH Chun, ...
2011 IEEE International Solid-State Circuits Conference, 494-496, 2011
192011
BAG2: A process-portable framework for generator-based AMS circuit design
E Chang, J Han, W Bae, Z Wang, N Narevsky, B NikoliC, E Alon
2018 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2018
152018
Design techniques for a 60 Gb/s 173 mW wireline receiver frontend in 65 nm CMOS technology
J Han, Y Lu, N Sutardja, K Jung, E Alon
IEEE Journal of Solid-State Circuits 51 (4), 871-880, 2016
142016
6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology
J Han, Y Lu, N Sutardja, E Alon
2017 IEEE International Solid-State Circuits Conference (ISSCC), 112-113, 2017
132017
A 60Gb/s 173mW receiver frontend in 65nm CMOS technology
J Han, Y Lu, N Sutardja, K Jung, E Alon
2015 Symposium on VLSI Circuits (VLSI Circuits), C230-C231, 2015
112015
Design techniques for a 60-Gb/s 288-mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65-nm CMOS technology
J Han, N Sutardja, Y Lu, E Alon
IEEE Journal of Solid-State Circuits 52 (12), 3474-3485, 2017
102017
A supply-scalable-serializing transmitter with controllable output swing and equalization for next-generation standards
W Bae, H Ju, K Park, J Han, DK Jeong
IEEE Transactions on Industrial Electronics 65 (7), 5979-5989, 2017
82017
4-Slot, 8-Drop Impedance-Matched Bidirectional Multidrop DQ Bus With a 4.8-Gb/s Memory Controller Transceiver
WY Shin, GM Hong, H Lee, JD Han, KS Park, DH Lim, S Kim, D Shim, ...
IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (5 …, 2013
82013
A real-time, analog/digital co-designed 1.89-GHz bandwidth, 175-kHz resolution sparse spectral analysis RISC-V SoC in 16-nm FinFET
A Wang, W Bae, J Han, S Bailey, P Rigge, O Ocal, Z Wang, ...
ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018
32018
An Automated SerDes Frontend Generator Verified With a 16-nm Instance Achieving 15 Gb/s at 1.96 pJ/bit
E Chang, N Narevsky, J Han, E Alon
IEEE Solid-State Circuits Letters 1 (12), 245-248, 2018
22018
A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET
S Bailey, J Han, P Rigge, R Lin, E Chang, H Mao, Z Wang, C Markley, ...
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 285-288, 2018
22018
A 5-Gb/s digitally controlled 3-tap DFE receiver for serial communications
JD Han, WY Shin, WS Choi, JH Chun, S Kim, DK Jeong
2010 IEEE Asian Solid-State Circuits Conference, 1-4, 2010
22010
A real-time, 1.89-GHz bandwidth, 175-kHz resolution sparse spectral analysis RISC-V SoC in 16-nm FinFET
A Wang, W Bae, J Han, S Bailey, O Ocal, P Rigge, Z Wang, ...
IEEE Journal of Solid-State Circuits 54 (7), 1993-2008, 2019
12019
A generated 7GS/s 8b time-interleaved SAR ADC with 38.2 dB SNDR at Nyquist in 16nm CMOS FinFET
J Han, E Chang, S Bailey, Z Wang, W Bae, A Wang, N Narevsky, ...
2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019
12019
LED illuminating apparatus having enhanced quantity of light
J Han
US Patent 9,101,016, 2015
12015
A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit
N Sutardja, J Han, N Narevsky, E Alon
ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019
2019
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance
S Bailey, P Rigge, J Han, R Lin, EY Chang, H Mao, Z Wang, C Markley, ...
IEEE Journal of Solid-State Circuits 54 (10), 2786-2801, 2019
2019
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