Follow
Giovanni Causapruno
Giovanni Causapruno
MBA Candidate 2018, SDA Bocconi -- PhD 2016, Politecnico di Torino
Verified email at polito.it
Title
Cited by
Cited by
Year
Nanomagnet logic: an architectural level overview
M Vacca, M Graziano, J Wang, F Cairo, G Causapruno, G Urgese, A Biroli, ...
Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives, 223-256, 2014
372014
Logic-in-memory: A nano magnet logic implementation
M Cofano, G Santoro, M Vacca, D Pala, G Causapruno, F Cairo, F Riente, ...
2015 IEEE Computer Society Annual Symposium on VLSI, 286-291, 2015
322015
Logic-in-memory architecture made real
D Pala, G Causapruno, M Vacca, F Riente, G Turvani, M Graziano, ...
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1542-1545, 2015
322015
Reconfigurable systolic array: From architecture to physical design for NML
G Causapruno, F Riente, G Turvani, M Vacca, MR Roch, M Zamboni, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (11 …, 2016
222016
Protein alignment systolic array throughput optimization
G Causapruno, G Urgese, M Vacca, M Graziano, M Zamboni
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (1), 68-77, 2014
222014
A standard cell approach for MagnetoElastic NML circuits
D Giri, M Vacca, G Causapruno, W Rao, M Graziano, M Zamboni
Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale …, 2014
142014
Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive algorithms
M Cofano, M Vacca, G Santoro, G Causapruno, G Turvani, M Graziano
Integration 66, 153-163, 2019
102019
Modeling, design, and analysis of MagnetoElastic NML circuits
D Giri, M Vacca, G Causapruno, M Zamboni, M Graziano
IEEE Transactions on Nanotechnology 15 (6), 977-985, 2016
102016
Interleaving in systolic-arrays: A throughput breakthrough
G Causapruno, M Vacca, M Graziano, M Zamboni
IEEE Transactions on Computers 64 (7), 1940-1953, 2014
72014
Parallel and serial computation in nanomagnet logic: An overview
D Giri, G Causapruno, F Riente
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (8 …, 2018
62018
Modeling and Optimization of Embedded Systems
M Tranchero, E Bellocchia, D Boyang, G Causapruno, A Moré, ...
Politecnico di Torino, Department of Electronics and Telecommunication …, 2019
12019
Architectural Solutions for NanoMagnet Logic
G Causapruno
Politecnico di Torino, 2016
12016
High Speed VLSI Architecture for Finding the First W Maximum/Minimum Values
G Xiao, W Ahmad, SAA Zaidi, MR Roch, G Causapruno
Applications in Electronics Pervading Industry, Environment and Society …, 2016
12016
A Reconfigurable Array Architecture for NML
G Causapruno, U Garlando, F Cairo, M Zamboni, M Graziano
2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 99-104, 2016
2016
A Framework for Network-On-Chip comparison based on OpenSPARC T2 processor
G Causapruno, A Audero, S Tota, M Ruo Roch
Applications in Electronics Pervading Industry, Environment and Society …, 2016
2016
The system can't perform the operation now. Try again later.
Articles 1–15