Ivan Kourtev
Ivan Kourtev
Affiliazione sconosciuta
Email verificata su google.com
Citata da
Citata da
Timing optimization through clock skew scheduling
IS Kourtev, B Taskin, EG Friedman
Springer Science & Business Media, 2008
Clock skew scheduling for improved reliability via quadratic programming
IS Kourtev, EG Friedman
1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999
Delay insertion method in clock skew scheduling
B Taskin, IS Kourtev
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
A single latch, high speed double-edge triggered flip-flop (DETFF)
TA Johnson, IS Kourtev
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and …, 2001
Timing-driven physical design for VLSI circuits using resonant rotary clocking
B Taskin, J Wood, IS Kourtev
2006 49th IEEE International Midwest Symposium on Circuits and Systems 1 …, 2006
A 64-way VLIW/SIMD FPGA architecture and design flow
AK Jones, R Hoare, IS Kourtev, J Fazekas, D Kusic, J Foster, S Boddie, ...
Proceedings of the 2004 11th IEEE International Conference on Electronics …, 2004
Substrate coupling in digital circuits in mixed-signal smart-power systems
RM Secareanu, S Warner, S Seabridge, C Burke, J Becerra, TE Watrobski, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (1), 67-78, 2004
Reduced dynamic swing domino logic
R Mader, I Kourtev
Proceedings of the 13th ACM Great Lakes symposium on VLSI, 33-36, 2003
Simultaneous clock scheduling and buffered clock tree synthesis
IS Kourtev, EG Friedman
Proceedings of 1997 IEEE International Symposium on Circuits and Systems …, 1997
A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations
IS Kourtev, EG Friedman
Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No. 99TH8454 …, 1999
Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits
B Taskin, IS Kourtev
IEEE transactions on very large scale integration (VLSI) systems 12 (1), 12-27, 2004
Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew
B Taskin, IS Kourtev
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in …, 2002
Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits
R Mader, EG Friedman, A Litman, IS Kourtev
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat …, 2002
Synthesis of clock tree topologies to implement nonzero clock skew schedule
IS Kourtev, EG Friedman
IEE Proceedings-Circuits, Devices and Systems 146 (6), 321-326, 1999
The behavior of digital circuits under substrate noise in a mixed-signal smart-power environment
RM Secareanu, IS Kourtev, J Becerra, TE Watrobski, C Morton, W Staub, ...
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD …, 1999
Noise immunity of digital circuits in mixed-signal smart power systems
RM Secareanu, IS Kourtev, J Becerra, TE Watrobski, C Morton, W Staub, ...
Proceedings Ninth Great Lakes Symposium on VLSI, 314-317, 1999
Topological synthesis of clock trees for VLSI-based DSP systems
IS Kourtev, EG Friedman
1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and …, 1997
LURU: global-scope FPGA technology mapping with content-addressable memories
JM Lucas, R Hoare, IS Kourtev, AK Jones
Proceedings of the 2004 11th IEEE International Conference on Electronics …, 2004
Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits
B Taskin, IS Kourtev
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
Linear timing analysis of soc synchronous circuits with level-sensitive latches
B Taskin, IS Kourtev
15th Annual IEEE International ASIC/SOC Conference, 358-362, 2002
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