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Salvatore Levantino
Titolo
Citata da
Citata da
Anno
Frequency dependence on bias current in 5 GHz CMOS VCOs: Impact on tuning range and flicker noise upconversion
S Levantino, C Samori, A Bonfanti, SLJ Gierkink, AL Lacaita, V Boccuzzi
IEEE Journal of Solid-State Circuits 37 (8), 1003-1011, 2002
3832002
A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling
SLJ Gierkink, S Levantino, RC Frye, C Samori, V Boccuzzi
IEEE Journal of Solid-State Circuits 38 (7), 1148-1154, 2003
3542003
A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider
S Pellerano, S Levantino, C Samori, AL Lacaita
IEEE Journal of Solid-State Circuits 39 (2), 378-383, 2004
3272004
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-Integrated Jitter at 4.5-mW Power
D Tasca, M Zanuso, G Marzin, S Levantino, C Samori, AL Lacaita
IEEE Journal of Solid-State Circuits 46 (12), 2745-2758, 2011
2882011
Integrated frequency synthesizers for wireless systems
AL Lacaita, S Levantino, C Samori
Cambridge University Press, 2007
1462007
Phase noise in digital frequency dividers
S Levantino, L Romanò, S Pellerano, C Samori, AL Lacaita
IEEE Journal of Solid-State Circuits 39 (5), 775-784, 2004
1462004
AM-to-PM conversion in varactor-tuned oscillators
S Levantino, C Samori, A Zanchi, AL Lacaita
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2002
1272002
An adaptive pre-distortion technique to mitigate the DTC nonlinearity in digital PLLs
S Levantino, G Marzin, C Samori
IEEE Journal of Solid-State Circuits 49 (8), 1762-1772, 2014
1222014
A 20 Mb/s phase modulator based on a 3.6 GHz digital PLL with− 36 dB EVM at 5 mW power
G Marzin, S Levantino, C Samori, AL Lacaita
IEEE Journal of Solid-State Circuits 47 (12), 2974-2988, 2012
1222012
Noise analysis and minimization in bang-bang digital PLLs
M Zanuso, D Tasca, S Levantino, A Donadel, C Samori, AL Lacaita
IEEE Transactions on Circuits and Systems II: Express Briefs 56 (11), 835-839, 2009
1202009
A wideband 3.6 GHz digital ΔΣ fractional-n pll with phase interpolation divider and digital spur cancellation
M Zanuso, S Levantino, C Samori, AL Lacaita
Solid-State Circuits, IEEE Journal of 46 (3), 627-638, 2011
1092011
Multiphase LC oscillators
L Romano, S Levantino, C Samori, AL Lacaita
IEEE Transactions on Circuits and Systems I: Regular Papers 53 (7), 1579-1588, 2006
1072006
Phase noise and accuracy in quadrature oscillators
L Romano, S Levantino, A Bonfanti, C Samori, AL Lacaita
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004
882004
A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop
A Zanchi, C Samori, S Levantino, AL Lacaita
IEEE Journal of Solid-State Circuits 36 (4), 611-619, 2001
882001
A-94 dBc/Hz@ 100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications
C Samori, S Levantino, V Boccuzzi
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No …, 2001
842001
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
A Santiccioli, M Mercandelli, L Bertulessi, A Parisi, D Cherniak, AL Lacaita, ...
IEEE Journal of Solid-State Circuits 55 (12), 3349-3361, 2020
792020
A 23-GHz low-phase-noise digital bang–bang PLL for fast triangular and sawtooth chirp modulation
D Cherniak, L Grimaldi, L Bertulessi, R Nonis, C Samori, S Levantino
IEEE Journal of Solid-State Circuits 53 (12), 3565-3575, 2018
792018
21.1 A 1.7 GHz MDLL-based fractional-N frequency synthesizer with 1.4 ps RMS integrated jitter and 3mW power using a 1b TDC
G Marucci, A Fenaroli, G Marzin, S Levantino, C Samori, AL Lacaita
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
732014
Time-to-digital converter for frequency synthesis based on a digital bang-bang DLL
M Zanuso, P Madoglio, S Levantino, C Samori, AL Lacaita
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (3), 548-555, 2009
712009
A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter
M Mercandelli, A Santiccioli, A Parisi, L Bertulessi, D Cherniak, AL Lacaita, ...
IEEE Journal of Solid-State Circuits 57 (2), 505-517, 2021
702021
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