Two‐Dimensional Mott Insulators in SrVO3 Ultrathin Films M Gu, SA Wolf, J Lu
Advanced Materials Interfaces 1 (7), 1300126, 2014
76 2014 Li2CuTi3O8–Li4Ti5O12 double spinel anode material with improved rate performance for Li-ion batteries D Wang, HY Xu, M Gu, CH Chen
Electrochemistry Communications 11 (1), 50-53, 2009
56 2009 Metal-insulator transition induced in CaVO3 thin films M Gu, J Laverock, B Chen, KE Smith, SA Wolf, J Lu
Journal of Applied Physics 113 (13), 2013
42 2013 Resonant Soft-X-Ray Emission as a Bulk Probe of Correlated Electron Behavior in Metallic J Laverock, B Chen, KE Smith, RP Singh, G Balakrishnan, M Gu, JW Lu, ...
Physical Review Letters 111 (4), 047402, 2013
25 2013 Metal-insulator transition in SrTi1− x Vx O3 thin films M Gu, SA Wolf, J Lu
Applied Physics Letters 103 (22), 223110, 2013
24 2013 Microstructural and domain effects in epitaxial CoFe2O4 films on MgO with perpendicular magnetic anisotropy R Comes, M Gu, M Khokhlov, J Lu, SA Wolf
Journal of Magnetism and Magnetic Materials 324 (4), 524-527, 2012
24 2012 Electron molecular beam epitaxy: Layer-by-layer growth of complex oxides via pulsed electron-beam deposition R Comes, M Gu, M Khokhlov, H Liu, J Lu, SA Wolf
Journal of Applied Physics 113 (2), 2013
22 2013 Hybrid low-k spacer scheme for advanced FinFET technology parasitic capacitance reduction M Gu, X Wang, W Li, M Aquilino, J Peng, H Wang, D Jaeger, K Tabakman, ...
Electronics Letters 56 (10), 514-516, 2020
11 2020 FinFET with contact over active-gate for 5G ultra-wideband applications A Razavieh, V Mahajan, WL Oo, S Cimino, SV Khokale, K Nagahiro, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
9 2020 Nano-engineering of electron correlation in oxide superlattices J Laverock, M Gu, V Jovic, JW Lu, SA Wolf, RM Qiao, W Yang, KE Smith
Nano Futures 1 (3), 031001, 2017
8 2017 Transport phenomena in SrVO3/SrTiO3 superlattices M Gu, SA Wolf, J Lu
Journal of Physics D: Applied Physics 51 (10), 10LT01, 2018
7 2018 Extremely-low threshold voltage FinFET for 5G mmWave applications A Razavieh, Y Chen, T Ethirajan, M Gu, S Cimino, T Shimizu, MK Hassan, ...
IEEE Journal of the Electron Devices Society 9, 165-169, 2020
6 2020 Forming a more robust sidewall spacer with lower k (dielectric constant) value T Han, M Gu, S Grunow, H Liu, S Sankaran, J Liu
2017 China Semiconductor Technology International Conference (CSTIC), 1-3, 2017
3 2017 Formation of epi source/drain material on transistor devices and the resulting structures M Gu, T Han
US Patent 10,777,463, 2020
2 2020 Epitaxial structures of a semiconductor device having a wide gate pitch MV Aquilino, D Jaeger, M Gu, B Morgenfeld, H Wang, KS Duggimpudi, ...
US Patent 10,971,625, 2021
1 2021 Lateral bipolar transistor M Gu, H Wang, J Singh
US Patent 11,843,034, 2023
2023 Bipolar junction transistors including a stress liner M Gu, J Singh, H Wang, J Johnson
US Patent 11,721,722, 2023
2023 Integrated circuit structure including asymmetric, recessed source and drain region and method for forming same M Gu, W Li
US Patent 11,532,745, 2022
2022 LDMOS finFET structure with buried insulator layer and method for forming same W Li, M Gu
US Patent 11,410,998, 2022
2022 Transistors with hybrid source/drain regions W Li, M Gu
US Patent 11,374,002, 2022
2022