| A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size S Natarajan, M Agostinelli, S Akbar, M Bost, A Bowonder, V Chikarmane, ... 2014 IEEE international electron devices meeting, 3.7. 1-3.7. 3, 2014 | 753 | 2014 |
| Stressed multidirectional solid-phase epitaxial growth of Si NG Rudawski, KS Jones, S Morarka, ME Law, RG Elliman Journal of Applied Physics 105 (8), 2009 | 60 | 2009 |
| Stability of polycrystalline silicon‐on‐cobalt disilicide–silicon structures SP Murarka, CC Chang, AC Adams Journal of Vacuum Science & Technology B: Microelectronics Processing and …, 1987 | 39 | 1987 |
| Modeling two-dimensional solid-phase epitaxial regrowth using level set methods S Morarka, NG Rudawski, ME Law, KS Jones, RG Elliman Journal of Applied Physics 105 (5), 2009 | 34 | 2009 |
| Level set modeling of the orientation dependence of solid phase epitaxial regrowth S Morarka, NG Rudawski, ME Law Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2008 | 25 | 2008 |
| Implementation of high power RF devices with hybrid workfunction and OxideThickness in 22nm low-power FinFET technology HJ Lee, S Morarka, S Rami, Q Yu, M Weiss, G Liu, M Armstrong, CY Su, ... 2019 IEEE International Electron Devices Meeting (IEDM), 25.4. 1-25.4. 4, 2019 | 21 | 2019 |
| Methods of forming dislocation enhanced strain in NMOS structures M Jackson, A Murthy, G Glass, S Morarka, C Mohapatra US Patent 10,396,201, 2019 | 10 | 2019 |
| Effect of n-and p-type dopants on patterned amorphous regrowth S Morarka, NG Rudawski, ME Law, KS Jones, RG Elliman Journal of Vacuum Science & Technology B 28 (1), C1F1-C1F5, 2010 | 10 | 2010 |
| A 2-D model for the potential distribution and threshold voltage of fully depleted short-channel ion-implanted silicon MESFET's S Jit, S Morarka, S Mishra JSTS: Journal of Semiconductor Technology and Science 5 (3), 173-181, 2005 | 10 | 2005 |
| Interface stability in stressed solid-phase epitaxial growth S Morarka, S Jin, NG Rudawski, KS Jones, ME Law, RG Elliman Journal of Vacuum Science & Technology B 29 (4), 2011 | 9 | 2011 |
| mmWave and sub-THz technology development in Intel 22nm FinFET (22FFL) process Q Yu, S Rami, J Waldemer, Y Ma, V Neeli, J Garrett, G Liu, J Koo, ... 2020 IEEE International Electron Devices Meeting (IEDM), 17.4. 1-17.4. 4, 2020 | 8 | 2020 |
| An E-band power amplifier using high power RF device with hybrid work function and oxide thickness in 22nm low-power FinFET Q Yu, YS Yeh, J Garret, J Koo, S Morarka, S Rami, G Liu, HJ Lee 2020 IEEE/MTT-S International Microwave Symposium (IMS), 999-1002, 2020 | 5 | 2020 |
| Field-effect transistors with asymmetric gate stacks S Rami, HJ Lee, S Morarka, G Liu, Q Yu, B Sell, M Armstrong US Patent 11,515,424, 2022 | 4 | 2022 |
| Resistance reduction under transistor spacers CE Weber, S Morarka, R Jhaveri, GA Glass, AS Murthy US Patent App. 15/754,150, 2018 | 3 | 2018 |
| Integrated circuit structures having cut metal gates with dielectric spacer fill LP Guler, C Munasinghe, M ABD EL QADER, M Conte, S Morarka, ... US Patent App. 17/348,000, 2022 | 2 | 2022 |
| APPLIED PHYSICS REVIEWS—FOCUSED REVIEW A Rogalski, J Antoszewski, L Faraone Journal of Applied Physics 105, 091101, 2009 | 2 | 2009 |
| FinFET varactor quality factor improvement HJ Lee, M Armstrong, S Morarka, C Nieva-lozano, KAR Ayan US Patent 11,961,836, 2024 | 1 | 2024 |
| Gate-all-around integrated circuit structures including varactors KAR Ayan, S Morarka, C Nieva-lozano, K Kolluru, B Guha, CH Lin, ... US Patent 11,869,987, 2024 | | 2024 |
| Varactor device with backside electrical contact KAR Ayan, KC Kolluru, NA Thomson, VB Neeli, S Rami, S Morarka, ... US Patent App. 17/848,660, 2023 | | 2023 |
| Partial gate cut structures in an integrated circuit LP Guler, T Ghani, S Morarka, CH Wallace US Patent App. 17/697,129, 2023 | | 2023 |
