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Christophe LALLEMENT
Christophe LALLEMENT
Professor, ICube Laboratory, University of Strasbourg / CNRS
Email verificata su unistra.fr
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Citata da
Citata da
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VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems
F Pêcheux, C Lallement, A Vachoux
IEEE transactions on Computer-Aided design of integrated Circuits and …, 2005
2932005
Charge-based modeling of junctionless double-gate field-effect transistors
JM Sallese, N Chevillon, C Lallement, B Iniguez, F Prégaldiny
IEEE Transactions on Electron Devices 58 (8), 2628-2637, 2011
2642011
CNTFET modeling and reconfigurable logic-circuit design
I O'Connor, J Liu, F Gaffiot, F Prégaldiny, C Lallement, C Maneux, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2365-2379, 2007
2192007
A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism
JM Sallese, F Krummenacher, F Prégaldiny, C Lallement, A Roy, C Enz
Solid-State Electronics 49 (3), 485-489, 2005
2102005
An efficient parameter extraction methodology for the EKV MOST model
M Bucher, C Lallement, CC Enz
Proceedings of International Conference on Microelectronic Test Structures …, 1996
1311996
The EPFL-EKV MOSFET model equations for simulation
M Bucher, C Lallement, C Enz, F Théodoloz, F Krummenacher
Version 2.6, 1998
1291998
A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs
F Prégaldiny, C Lallement, D Mathiot
Solid-State Electronics 46 (12), 2191-2198, 2002
742002
Accounting for quantum mechanical effects from accumulation to inversion, in a fully analytical surface-potential-based MOSFET model
F Prégaldiny, C Lallement, D Mathiot
Solid-State Electronics 48 (5), 781-787, 2004
702004
Explicit compact model for symmetric double-gate MOSFETs including solutions for small-geometry effects
B Diagne, F Prégaldiny, C Lallement, JM Sallese, F Krummenacher
Solid-State Electronics 52 (1), 99-106, 2008
692008
Design-oriented compact models for CNTFETs
F Pregaldiny, C Lallement, JB Kammerer
International Conference on Design and Test of Integrated Systems in …, 2006
632006
Accurate MOS modelling for analog circuit simulation using the EKV model
M Bucher, C Lallement, C Enz, F Krummenacher
1996 IEEE International Symposium on Circuits and Systems. Circuits and …, 1996
581996
A common core model for junctionless nanowires and symmetric double-gate FETs
JM Sallese, F Jazaeri, L Barbut, N Chevillon, C Lallement
IEEE transactions on electron devices 60 (12), 4277-4280, 2013
542013
Generalization of the concept of equivalent thickness and capacitance to multigate MOSFETs modeling
N Chevillon, JM Sallese, C Lallement, F Prégaldiny, M Madec, J Sedlmeir, ...
IEEE Transactions on Electron Devices 59 (1), 60-71, 2011
542011
An advanced explicit surface potential model physically accounting for the quantization effects in deep-submicron MOSFETs
F Prégaldiny, C Lallement, R van Langevelde, D Mathiot
Solid-State Electronics 48 (3), 427-435, 2004
532004
Physics-based compact model for ultra-scaled FinFETs
A Yesayan, F Prégaldiny, N Chevillon, C Lallement, JM Sallese
Solid-State Electronics 62 (1), 165-173, 2011
522011
Improved analytical modeling of polysilicon depletion in MOSFETs for circuit simulation
JM Sallese, M Bucher, C Lallement
Solid-State Electronics 44 (6), 905-912, 2000
522000
The EPFL-EKV MOSFET model equations for simulation, Version 2.6
M Bucher, C Lallement, C Enz, F Théodoloz, F Krummenacher
Technical Report, EPFL, 1997
461997
The EKV 3.0 compact MOS transistor model: accounting for deep-submicron aspects
M Bucher, C Enz, F Krummenacher, JM Sallese, C Lallement, AS Porret
Proc. MSM Int. Conf., Nanotech 2002, 670-673, 2002
452002
Modelling and characterization of non-uniform substrate doping
C Lallement, M Bucher, C Enz
Solid-State Electronics 41 (12), 1857-1861, 1997
421997
Scalable Gm/I based MOSFET model
M Bucher, C Lallement, C Enz, F Théodoloz, F Krummenacher
Int. Semicond. Dev. Research Symp.(ISDRS’97), 615-618, 1997
391997
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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