| A capacitance-based methodology for work function extraction of metals on high-/spl kappa R Jha, J Gurganos, YH Kim, R Choi, J Lee, V Misra IEEE Electron Device Letters 25 (6), 420-423, 2004 | 137 | 2004 |
| A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, ... 2008 symposium on vlsi technology, 88-89, 2008 | 130 | 2008 |
| Dual metal and dual dielectric integration for metal high-K FETs MP Chudzik, WK Henson, R Jha, Y Liang, R Ramachandran, RS Wise US Patent 8,436,427, 2013 | 123 | 2013 |
| Novel synaptic memory device for neuromorphic computing S Mandal, A El-Amin, K Alexander, B Rajendran, R Jha Scientific reports 4 (1), 5333, 2014 | 116 | 2014 |
| Switching Characteristics ofRRAM Devices for Digital and Analog Nonvolatile Memory Applications B Long, Y Li, R Jha IEEE Electron Device Letters 33 (5), 706-708, 2012 | 70 | 2012 |
| Switching characteristics of W/Zr/HfO2/TiN ReRAM devices for multi-level cell non-volatile memory applications W Chen, W Lu, B Long, Y Li, D Gilmer, G Bersuker, S Bhunia, R Jha Semiconductor Science and Technology 30 (7), 075002, 2015 | 58 | 2015 |
| Gate controlled three-terminal metal oxide memristor E Herrmann, A Rush, T Bailey, R Jha IEEE Electron Device Letters 39 (4), 500-503, 2018 | 50 | 2018 |
| Switching dynamics and charge transport studies of resistive random access memory devices B Long, Y Li, S Mandal, R Jha, K Leedy Applied Physics Letters 101 (11), 2012 | 43 | 2012 |
| Semiconductor device having dual metal gates and method of manufacture U Kwon, SA Krishnan, T Ando, MP Chudzik, MM Frank, WK Henson, ... US Patent 7,838,908, 2010 | 42 | 2010 |
| Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS JH Lee, YS Suh, H Lazar, R Jha, J Gurganus, Y Lin, V Misra IEEE International Electron Devices Meeting 2003, 13.5. 1-13.5. 4, 2003 | 37 | 2003 |
| Effects of Mg-Doping on -Based ReRAM Device Switching Characteristics BM Long, S Mandal, J Livecchi, R Jha IEEE electron device letters 34 (10), 1247-1249, 2013 | 35 | 2013 |
| Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate K Henson, H Bu, MH Na, Y Liang, U Kwon, S Krishnan, J Schaeffer, R Jha, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 34 | 2008 |
| Unsupervised clustering of COVID-19 chest X-ray images with a self-organizing feature map B King, S Barve, A Ford, R Jha 2020 IEEE 63rd international midwest symposium on circuits and systems …, 2020 | 29 | 2020 |
| Dual metal and dual dielectric integration for metal high-k FETs MP Chudzik, WK Henson, R Jha, Y Liang, R Ramachandran, RS Wise US Patent 7,943,457, 2011 | 28 | 2011 |
| Work function tuning via interface dipole by ultrathin reaction layers using AlTa and AlTaN alloys B Chen, R Jha, V Misra IEEE electron device letters 27 (9), 731-733, 2006 | 28 | 2006 |
| Nanoelectric memristor device with dilute magnetic semiconductors R Jha, J Ordosgoitti, B Long US Patent 8,502,343, 2013 | 24 | 2013 |
| Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors H Bu, MP Chudzik, W He, R Jha, YH Kim, SA Krishnan, RT Mo, ... US Patent App. 12/414,794, 2010 | 24 | 2010 |
| Structure and method to control oxidation in high-k gate structures WC Natzle, RT Mo, R Jha, KT Schonenberg, RA Conti US Patent 7,955,926, 2011 | 23 | 2011 |
| Gate effective-workfunction modification for CMOS DG Park, MP Chudzik, R Jha, SA Krishnan, N Moumen, V Narayanan, ... US Patent 7,947,549, 2011 | 22 | 2011 |
| Method for tuning the threshold voltage of a metal gate and high-k device MP Chudzik, MA Gribelyuk, R Jha, RT Mo, N Moumen, KKH Wong US Patent 7,754,594, 2010 | 21 | 2010 |
Veena MisraNorth Carolina State UniversityVerified email at ncsu.edu
