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Judson Holt
Judson Holt
Email verificata su us.ibm.com
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Citata da
Anno
Ultra-thin body super-steep retrograde well (SSRW) FET devices
DC Boyd, JR Holt, M Ieong, RT Mo, Z Ren, GG Shahidi
US Patent 7,002,214, 2006
1902006
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
P Agnello, T Ivers, C Warm, R Wise, R Wachnik, D Schepis, S Sankaran, ...
2006 International Electron Devices Meeting, 1-4, 2006
1332006
Structure and method for mobility enhanced MOSFETs with unalloyed silicide
Y Liu, D Chidambarrao, O Gluschenkov, JR Holt, RT Mo, K Rim
US Patent 8,217,423, 2012
1312012
Structure and method for mobility enhanced MOSFETs with unalloyed silicide
Y Liu, D Chidambarrao, O Gluschenkov, JR Holt, RT Mo, K Rim
US Patent 8,217,423, 2012
1312012
Structure and method for mobility enhanced MOSFETs with unalloyed silicide
Y Liu, D Chidambarrao, O Gluschenkov, JR Holt, RT Mo, K Rim
US Patent 8,217,423, 2012
1312012
Chemical treatment to retard diffusion in a semiconductor overlayer
KK Chan, H Chen, MA Gribelyuk, JR Holt, WH Lee, RM Mitchell, RT Mo, ...
US Patent 7,071,103, 2006
1222006
Method to control source/drain stressor profiles for stress engineering
YF Chong, Z Luo, JR Holt
US Patent 8,017,487, 2011
1152011
Stressed field effect transistors on hybrid orientation substrate
D Chidambarrao, JR Holt, M Ieong, OC Ouyang, S Panda
US Patent 7,405,436, 2008
1142008
High-resolution three-dimensional structural microscopy by single-angle Bragg ptychography
SO Hruszkewycz, M Allain, MV Holt, CE Murray, JR Holt, PH Fuoss, ...
Nature materials 16 (2), 244-251, 2017
1112017
Stressed field effect transistors on hybrid orientation substrate
D Chidambarrao, JR Holt, M Ieong, OC Ouyang, S Panda
US Patent 7,405,436, 2008
1072008
Formation of raised source/drain structures in NFET with embedded SiGe in PFET
YF Chong, Z Luo, JC Kim, JR Holt
US Patent 7,718,500, 2010
1042010
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
S Narasimha, P Chang, C Ortolland, D Fried, E Engbrecht, K Nummy, ...
2012 International Electron Devices Meeting, 3.3. 1-3.3. 4, 2012
1032012
Metal oxide field effect transistor with a sharp halo
H Chen, JR Holt, R Jagannathan, WC Natzle, MR Sievers, RS Wise
US Patent 7,859,013, 2010
1022010
Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain
K Cheng, A Khakifirooz, P Kulkarni, S Kanakasabapathy, S Schmitz, ...
2009 Symposium on VLSI Technology, 212-213, 2009
962009
Quantitative nanoscale imaging of lattice distortions in epitaxial semiconductor heterostructures using nanofocused X-ray Bragg projection ptychography
SO Hruszkewycz, MV Holt, CE Murray, J Bruley, J Holt, A Tripathi, ...
Nano letters 12 (10), 5148-5154, 2012
952012
Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies
LT Su, J Pellerin, SF Huang, M Khare, D Schepis, K Rim, S Liming, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005
932005
Stress enhanced transistor devices and methods of making
TN Adam, JR Holt, TA Wallner
US Patent App. 12/136,195, 2009
852009
Material for contact etch layer to enhance device performance
AB Chakravarti, S Narasimha, V Chan, J Holt, SN Chakravarti
US Patent 7,001,844, 2006
782006
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
WH Lee, A Waite, H Nii, HM Nayfeh, V McGahay, H Nakayama, D Fried, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 4 …, 2005
692005
A 7nm CMOS technology platform for mobile and high performance compute application
S Narasimha, B Jagannathan, A Ogino, D Jaeger, B Greene, C Sheraw, ...
2017 IEEE International Electron Devices Meeting (IEDM), 29.5. 1-29.5. 4, 2017
642017
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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