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Pasquale Davide Schiavone
Pasquale Davide Schiavone
EPFL, OpenHW Group
Email verificata su epfl.ch
Titolo
Citata da
Citata da
Anno
Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices
M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ...
IEEE transactions on very large scale integration (VLSI) systems 25 (10 …, 2017
5362017
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
PD Schiavone, F Conti, D Rossi, M Gautschi, A Pullini, E Flamand, ...
2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017
2862017
An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics
F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017
1622017
XNOR neural engine: A hardware accelerator IP for 21.6-fJ/op binary neural network inference
F Conti, PD Schiavone, L Benini
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
1612018
Quentin: an ultra-low-power pulpissimo soc in 22nm fdx
PD Schiavone, D Rossi, A Pullini, A Di Mauro, F Conti, L Benini
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
1012018
A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems
VJ Kartsch, S Benatti, PD Schiavone, D Rossi, L Benini
Information Fusion 43, 66-76, 2018
772018
Fast and accurate multiclass inference for MI-BCIs using large multiscale temporal and spectral features
M Hersche, T Rellstab, PD Schiavone, L Cavigelli, L Benini, A Rahimi
2018 26th European Signal Processing Conference (EUSIPCO), 1690-1694, 2018
682018
Arnold: An eFPGA-augmented RISC-V SoC for flexible and low-power IoT end nodes
PD Schiavone, D Rossi, A Di Mauro, FK Gürkaynak, T Saxe, M Wang, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 677-690, 2021
602021
Always-on 674μ W@ 4GOP/s error resilient binary neural networks with aggressive SRAM voltage scaling on a 22-nm IoT end-node
A Di Mauro, F Conti, PD Schiavone, D Rossi, L Benini
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3905-3918, 2020
442020
RI5CY: User manual
A Traber, M Gautschi, PD Schiavone
Micrel Lab and Multitherman Lab University of Bologna: Bologna Italy, 2019
262019
An evolutionary approach for test program compaction
R Cantoro, M Gaudesi, E Sanchez, PD Schiavone, G Squillero
2015 16th Latin-American Test Symposium (LATS), 2015
25*2015
X-heep: An open-source, configurable and extendible risc-v microcontroller for the exploration of ultra-low-power edge accelerators
S Machetti, PD Schiavone, TC Müller, M Peón-Quirós, D Atienza
arXiv preprint arXiv:2401.05548, 2024
232024
On-line testing for autonomous systems driven by risc-v processor design verification
A Ruospo, R Cantoro, E Sanchez, PD Schiavone, A Garofalo, L Benini
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2019
202019
An open-source verification framework for open-source cores: A RISC-V case study
PD Schiavone, E Sanchez, A Ruospo, F Minervini, F Zaruba, G Haugou, ...
2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018
192018
Pushing on-chip memories beyond reliability boundaries in micropower machine learning applications
A Di Mauro, F Conti, PD Schiavone, D Rossi, L Benini
2019 IEEE International Electron Devices Meeting (IEDM), 30.4. 1-30.4. 4, 2019
92019
X-heep: An open-source, configurable and extendible RISC-V microcontroller
PD Schiavone, S Machetti, M Peón-Quirós, J Miranda, B Denkinger, ...
Proceedings of the 20th ACM International Conference on Computing Frontiers …, 2023
82023
Tiny-FPU: low-cost floating-point support for small RISC-V MCU cores
L Bertaccini, M Perotti, S Mach, PD Schiavone, F Zaruba, L Benini
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
82021
HW/SW approaches for RISC-V code size reduction
M Perotti, PD Schiavone, G Tagliavini, D Rossi, T Kurd, M Hill, L Yingying, ...
Workshop on Computer Architecture Research with RISC-V (CARRV 2020), 2020
72020
sEMG neural spikes reconstruction for gesture recognition on a low-power multicore processor
M Orlandi, M Zanghieri, VJK Morinigo, F Conti, D Schiavone, L Benini, ...
2022 IEEE Biomedical Circuits and Systems Conference (BioCAS), 704-708, 2022
62022
From swift to mighty: A cost-benefit analysis of ibex and CV32E40P regarding application performance, power and area
N Gallmann, P Vogel, PD Schiavone, L Benini
5th Workshop Comput. Archit. Res. With RISC-V (CARRV), 2021
62021
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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