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Jamie Garside
Jamie Garside
PhD Student, Real Time Systems Research Group (RTSRG), Computer Science, University of York
Verified email at cs.york.ac.uk
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Cited by
Cited by
Year
T-CREST: Time-predictable multi-core architecture for embedded systems
M Schoeberl, S Abbaspour, B Akesson, N Audsley, R Capasso, J Garside, ...
Journal of Systems Architecture 61 (9), 449-471, 2015
2412015
A globally arbitrated memory tree for mixed-time-criticality systems
MD Gomony, J Garside, B Akesson, N Audsley, K Goossens
IEEE Transactions on Computers 66 (2), 212-225, 2016
352016
A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems
MD Gomony, J Garside, B Akesson, N Audsley, K Goossens
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 193-198, 2015
242015
Prefetching across a shared memory tree within a network-on-chip architecture
J Garside, NC Audsley
2013 International Symposium on System on Chip (SoC), 1-4, 2013
232013
Investigating shared memory tree prefetching within multimedia noc architectures
J Garside, NC Audsley
Memory Architecture and Organisation Workshop, 1-7, 2013
152013
Wcet preserving hardware prefetch for many-core real-time systems
J Garside, NC Audsley
Proceedings of the 22Nd International Conference on Real-Time Networks and …, 2014
92014
Transparent hardware synthesis of Java for predictable large-scale distributed systems
I Gray, Y Chan, J Garside, N Audsley, A Wellings
arXiv preprint arXiv:1508.07142, 2015
52015
FPGA-based hardware acceleration for real-time big data systems
I Gray, Y Chan, J Garside, NC Audsley, AJ Wellings
9th HiPEAC workshop on Reconfigurable Computing, 2015
32015
Real-Time Prefetching On Shared-Memory Multi-Core Systems
J Garside
University of York, 2015
12015
A reconfigurable mixed-time-criticality SDRAM controller
SLM Goossens
2015
Prefetching to Improve the Worst-case Execution Time of Real-Time Big-Data Tasks
J Garside, I Gray, NC Audsley
Workshop on Reconfigurable Computing for HPC and HPDA, 2015
2015
Adaptive Memory Scheduling Qualifying Dissertation
J Garside
2012
A 16-bit ISA for Microblaze Processors
J Garside
2011
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Articles 1–13