| An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks D Pani, P Meloni, G Tuveri, F Palumbo, P Massobrio, L Raffo Frontiers in neuroscience 11, 90, 2017 | 92 | 2017 |
| Cross-layer design of reconfigurable cyber-physical systems M Masin, F Palumbo, H Myrhaug, JA de Oliveira Filho, M Pastena, ... 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 740-745, 2017 | 38 | 2017 |
| The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms F Palumbo, N Carta, D Pani, P Meloni, L Raffo Journal of real-time image processing 9 (1), 233-249, 2014 | 35 | 2014 |
| The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems Z Al-Ars, T Basten, A de Beer, M Geilen, D Goswami, P Jääskeläinen, ... Proceedings of the 16th ACM International Conference on Computing Frontiers …, 2019 | 33 | 2019 |
| Power-awarness in coarse-grained reconfigurable multi-functional architectures: a dataflow based strategy F Palumbo, T Fanni, C Sau, P Meloni Journal of Signal Processing Systems 87 (1), 81-106, 2017 | 32 | 2017 |
| In-Field Automatic Detection of Grape Bunches under a Totally Uncontrolled Environment L Ghiani, A Sassu, F Palumbo, L Mercenaro, F Gambella Sensors 21 (11), 3908, 2021 | 31 | 2021 |
| Reconfigurable coprocessors synthesis in the MPEG-RVC domain C Sau, L Fanni, P Meloni, L Raffo, F Palumbo ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference …, 2015 | 29 | 2015 |
| An integrated hardware/software design methodology for signal processing systems L Li, C Sau, T Fanni, J Li, T Viitanen, F Christophe, F Palumbo, L Raffo, ... Journal of Systems Architecture 93, 1-19, 2019 | 27 | 2019 |
| Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing C Sau, F Palumbo, M Pelcat, J Heulot, E Nogues, D Menard, P Meloni, ... IEEE Embedded Systems Letters 9 (3), 65-68, 2017 | 23 | 2017 |
| Automated Design Flow for Multi-Functional Dataflow-Based Platforms C Sau, P Meloni, L Raffo, F Palumbo, E Bezati, S Casale-Brunet, ... Journal of Signal Processing Systems 85 (1), 143-165, 2016 | 23 | 2016 |
| Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach F Palumbo, T Fanni, C Sau, A Rodríguez, D Madroñal, K Desnos, ... International Conference on Embedded Computer Systems, 416-428, 2019 | 20 | 2019 |
| Power and clock gating modelling in coarse grained reconfigurable systems T Fanni, C Sau, P Meloni, L Raffo, F Palumbo Proceedings of the ACM International Conference on Computing Frontiers, 384-391, 2016 | 20 | 2016 |
| Multi-purpose systems: A novel dataflow-based generation and mapping strategy JF Nezan, N Siret, M Wipliez, F Palumbo, L Raffo Circuits and Systems (ISCAS), 2012 IEEE International Symposium on, 3073-3076, 2012 | 20 | 2012 |
| The multi-dataflow composer tool: A runtime reconfigurable hdl platform composer F Palumbo, N Carta, L Raffo Proceedings of the 2011 Conference on Design & Architectures for Signal …, 2011 | 20 | 2011 |
| A Composable Monitoring System for Heterogeneous Embedded Platforms G Valente, T Fanni, C Sau, TD Mascio, L Pomante, F Palumbo ACM Transactions on Embedded Computing Systems (TECS) 20 (5), 1-34, 2021 | 19 | 2021 |
| Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems T Fanni, A Rodríguez, C Sau, L Suriano, F Palumbo, L Raffo, E de la Torre 2018 International Conference on ReConFigurable Computing and FPGAs …, 2018 | 19 | 2018 |
| Coarse-grained reconfiguration: dataflow-based power management F Palumbo, C Sau, L Raffo Computers & Digital Techniques, IET 9 (1), 36-48, 2015 | 19 | 2015 |
| A coarse-grained reconfigurable wavelet denoiser exploiting the Multi-Dataflow Composer tool N Carta, C Sau, F Palumbo, D Pani, L Raffo Design and Architectures for Signal and Image Processing (DASIP), 2013 …, 2013 | 19 | 2013 |
| Introduction to the Tiled HW Architecture of SHAPES S PAOLUCCI P, F LO CICERO, A Lonardo, M Perra, D Rossetti, C Sidore, ... DATE 2007 Friday Workshop, 79-82, 2007 | 19 | 2007 |
| A coarse-grained reconfigurable approach for low-power spike sorting architectures N Carta, C Sau, D Pani, F Palumbo, L Raffo Neural Engineering (NER), 2013 6th International IEEE/EMBS Conference on …, 2013 | 18 | 2013 |
Mattavelli MarcoMER, Ecole Polytechnique Federale de Lausanne, EPFLEmail verificata su epfl.ch
