The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 251 | 2020 |
Colt: Coalesced large-reach tlbs B Pham, V Vaidyanathan, A Jaleel, A Bhattacharjee 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 258-269, 2012 | 247 | 2012 |
Increasing TLB reach by exploiting clustering in page translations B Pham, A Bhattacharjee, Y Eckert, GH Loh 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 182 | 2014 |
Large pages and lightweight memory management in virtualized environments: Can you have it both ways? B Pham, J Veselý, GH Loh, A Bhattacharjee Proceedings of the 48th International Symposium on Microarchitecture, 1-12, 2015 | 134 | 2015 |
Using tlb speculation to overcome page splintering in virtual machines B Pham, J Vesely, GH Loh, A Bhattacharjee Rutgers University, 2015 | 22 | 2015 |
TLB shootdown mitigation for low-power many-core servers with L1 virtual caches B Pham, D Hower, A Bhattacharjee, T Cain IEEE Computer Architecture Letters 17 (1), 17-20, 2017 | 17 | 2017 |
The gem5 simulator: Version 20.0+. CoRR abs/2007.03152 (2020) J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 12 | 2020 |
Valid bits of a translation lookaside buffer (TLB) for checking multiple page sizes in one probe cycle and reconfigurable sub-TLBS DP Keppel, B Pham US Patent 11,055,232, 2021 | 11 | 2021 |
Method and apparatus for multi-level memory early page demotion B Pham, CB Wilkerson, AR Alameldeen, ZA Chishti, Z Wang US Patent 10,860,244, 2020 | 11 | 2020 |
Method and system for performing data movement operations with read snapshot and in place write update A Vasudevan, V Krishnan, AJ Herdrich, R Wang, RG Blankenship, ... US Patent 10,606,755, 2020 | 9 | 2020 |
System, method, and apparatus for snapshot prefetching to improve performance of snapshot operations R Wang, LC Stewart, B Pham, A Herdrich, V Krishnan, A Vasudevan, ... US Patent App. 16/147,346, 2020 | 8 | 2020 |
Branch prediction based on coherence operations in processors C Wilkerson, B Pham, P Lu, JW Stark IV US Patent 10,521,236, 2019 | 4 | 2019 |
Apparatuses, methods, and systems to accelerate store processing B Pham, C Dan US Patent 10,754,782, 2020 | 3 | 2020 |
Method and system for performing data movement operations with read snapshot and in place write update A Vasudevan, V Krishnan, AJ Herdrich, R Wang, RG Blankenship, ... US Patent 11,327,894, 2022 | 1 | 2022 |
Programmable address range engine for larger region sizes E Farah, M Diamond, D Keppel, SS Sury, B Pham, S Vissapragada US Patent App. 16/786,815, 2020 | 1 | 2020 |
Architectural support for efficient virtual memory on big-memory systems BQ Pham Rutgers The State University of New Jersey, School of Graduate Studies, 2016 | 1 | 2016 |
Branch prediction based on coherence operations in processors C Wilkerson, B Pham, P Lu, JW Stark IV US Patent 11,886,884, 2024 | | 2024 |
Method and system for performing data movement operations with read snapshot and in place write update A Vasudevan, V Krishnan, AJ Herdrich, R Wang, RG Blankenship, ... US Patent 11,816,036, 2023 | | 2023 |
Method and system for leveraging non-uniform miss penality in cache replacement policy to improve processor performance and power BQ Pham, R Wang US Patent 10,496,551, 2019 | | 2019 |