| Plasticity in memristive devices for spiking neural networks S Saïghi, CG Mayr, T Serrano-Gotarredona, H Schmidt, G Lecerf, J Tomas, ... Frontiers in neuroscience 9, 51, 2015 | 245 | 2015 |
| Neuromorphic hardware in the loop: Training a deep spiking network on the brainscales wafer-scale system S Schmitt, J Klähn, G Bellec, A Grübl, M Guettler, A Hartel, S Hartmann, ... 2017 international joint conference on neural networks (IJCNN), 2227-2234, 2017 | 169 | 2017 |
| A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems D Brüderle, MA Petrovici, B Vogginger, M Ehrlich, T Pfeil, S Millner, ... Biological cybernetics 104, 263-296, 2011 | 140 | 2011 |
| Exploiting Memristive BiFeO3 Bilayer Structures for Compact Sequential Logics T You, Y Shuai, W Luo, N Du, D Bürger, I Skorupa, R Hübner, S Henker, ... Advanced Functional Materials 24 (22), 3357-3365, 2014 | 138 | 2014 |
| SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning C Mayr, S Hoeppner, S Furber Communicating Process Architectures CPA 2018 1, 277-280, 2018 | 105 | 2018 |
| A biological-realtime neuromorphic system in 28 nm CMOS using low-leakage switched capacitor circuits C Mayr, J Partzsch, M Noack, S Hänzsche, S Scholze, S Höppner, ... IEEE transactions on biomedical circuits and systems 10 (1), 243-254, 2015 | 104 | 2015 |
| Memristive synapses connect brain and silicon spiking neurons A Serb, A Corna, R George, A Khiat, F Rocchi, M Reato, M Maschietto, ... Scientific reports 10 (1), 2590, 2020 | 87 | 2020 |
| Live demonstration: A scaled-down version of the brainscales wafer-scale neuromorphic system J Schemmel, A Grübl, S Hartmann, A Kononov, C Mayr, K Meier, S Millner, ... 2012 IEEE international symposium on circuits and systems (ISCAS), 702-702, 2012 | 83 | 2012 |
| Single pairing spike-timing dependent plasticity in BiFeO3 memristors with a time window of 25 ms to 125 μs N Du, M Kiani, CG Mayr, T You, D Bürger, I Skorupa, OG Schmidt, ... Frontiers in neuroscience 9, 227, 2015 | 64 | 2015 |
| Memory-efficient deep learning on a SpiNNaker 2 prototype C Liu, G Bellec, B Vogginger, D Kappel, J Partzsch, F Neumärker, ... Frontiers in neuroscience 12, 840, 2018 | 60 | 2018 |
| A 32 GBit/s communication SoC for a waferscale neuromorphic system S Scholze, H Eisenreich, S Höppner, G Ellguth, S Henker, M Ander, ... Integration 45 (1), 61-75, 2012 | 53 | 2012 |
| Rate and pulse based plasticity governed by local synaptic state variables CG Mayr, J Partzsch Frontiers in Synaptic Neuroscience 2, 33, 2010 | 53 | 2010 |
| Implementation of a spike-based perceptron learning rule using TiO2−x memristors H Mostafa, A Khiat, A Serb, CG Mayr, G Indiveri, T Prodromakis Frontiers in neuroscience 9, 357, 2015 | 49 | 2015 |
| VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality S Scholze, S Schiefer, J Partzsch, S Hartmann, CG Mayr, S Höppner, ... Frontiers in neuroscience 5, 117, 2011 | 48 | 2011 |
| Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS M Noack, J Partzsch, CG Mayr, S Hänzsche, S Scholze, S Höppner, ... Frontiers in neuroscience 9, 10, 2015 | 46 | 2015 |
| Practical guide for validated memristance measurements N Du, Y Shuai, W Luo, C Mayr, R Schüffny, OG Schmidt, H Schmidt Review of Scientific Instruments 84 (2), 2013 | 44 | 2013 |
| A fixed point exponential function accelerator for a neuromorphic many-core system J Partzsch, S Höppner, M Eberlein, R Schüffny, C Mayr, DR Lester, ... 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 42 | 2017 |
| Nonvolatile Multilevel Resistive Switching in Irradiated Thin Films Y Shuai, X Ou, W Luo, N Du, C Wu, W Zhang, D Burger, C Mayr, ... IEEE Electron Device Letters 34 (1), 54-56, 2012 | 42 | 2012 |
| Efficient reward-based structural plasticity on a SpiNNaker 2 prototype Y Yan, D Kappel, F Neumärker, J Partzsch, B Vogginger, S Höppner, ... IEEE transactions on biomedical circuits and systems 13 (3), 579-591, 2019 | 40 | 2019 |
| A heterogeneous SDR MPSoC in 28 nm CMOS for low-latency wireless applications S Haas, T Seifert, B Nöthen, S Scholze, S Höppner, A Dixius, EP Adeva, ... Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 36 | 2017 |
Johannes PartzschChair for Highly Parallel VLSI Systems and Neuromorphic Circuits, TU DresdenVerified email at tu-dresden.de
