Xin Miao
Xin Miao
IBM Research
Email verificata su us.ibm.com
Titolo
Citata da
Citata da
Anno
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ...
2017 Symposium on VLSI Technology, T230-T231, 2017
2622017
Stacked nanowires
Z Bi, K Cheng, J Li, X Miao
US Patent App. 10/170,331, 2019
146*2019
Silicon germanium fin immune to epitaxy defect
K Cheng, J Li, X Miao
US Patent App. 10/079,302, 2018
118*2018
Nanosheet MOSFET with full-height air-gap spacer
K Cheng, BB Doris, MA Guillorn, X Miao
US Patent 9,362,355, 2016
962016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ...
2016 IEEE International Electron Devices Meeting (IEDM), 2.7. 1-2.7. 4, 2016
892016
Fabrication of a vertical fin field effect transistor (vertical finFET) with a self-aligned gate and fin edges
K Cheng, X Miao, XU Wenyu, C Zhang
US Patent App. 10/103,246, 2018
85*2018
Site-controlled VLS Growth of Planar Nanowires: Yield and Mechanism
C Zhang, X Miao, PK Mohseni, W Choi, X Li
Nano letters 14 (12), 6836-6841, 2014
612014
Field effect transistor air-gap spacers with an etch-stop layer
K Cheng, X Miao, XU Wenyu, C Zhang
US Patent App. 10/134,866, 2018
59*2018
High-speed planar GaAs nanowire arrays with fmax> 75 GHz by wafer-scale bottom-up growth
X Miao, K Chabak, C Zhang, P Katal Mohseni, D Walker Jr, X Li
Nano letters, 2014
522014
Vertical field effect transistors with uniform threshold voltage
K Cheng, X Miao, H Wu, P Xu
US Patent App. 10/170,590, 2019
44*2019
Scalable monolithically grown AlGaAs–GaAs planar nanowire high-electron-mobility transistor
X Miao, X Li
IEEE Electron Device Letters 32 (9), 1227-1229, 2011
412011
Monolithic barrier-all-around high electron mobility transistor with planar GaAs nanowire channel
X Miao, C Zhang, X Li
Nano letters 13 (6), 2548-2552, 2013
372013
Vertical FETs with different gate lengths and spacer thicknesses
X Miao, K Cheng, C Zhang, XU Wenyu
US Patent App. 10/141,448, 2018
34*2018
Vertical field effect transistors with bottom source/drain epitaxy
K Cheng, X Miao, XU Wenyu, C Zhang
US Patent App. 10/134,874, 2018
34*2018
Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
BB Doris, MA Guillorn, I Lauer, X Miao
US Patent 9,647,139, 2017
342017
Stacked nanowires
Z Bi, K Cheng, J Li, X Miao
US Patent 9,716,142, 2017
332017
Air gap spacer between contact and gate region
K Cheng, NJ Loubet, X Miao, A Reznicek
US Patent 9,716,158, 2017
272017
Air spacer for 10nm FinFET CMOS and beyond
K Cheng, C Park, C Yeung, S Nguyen, J Zhang, X Miao, M Wang, ...
2016 IEEE International Electron Devices Meeting (IEDM), 17.1. 1-17.1. 4, 2016
262016
Gate length controlled vertical FETs
K Cheng, X Miao, XU Wenyu, C Zhang
US Patent 10,153,367, 2018
252018
Gate-to-bulk substrate isolation in gate-all-around devices
JB Chang, MA Guillorn, I Lauer, X Miao
US Patent App. 10/170,636, 2019
24*2019
Il sistema al momento non pu eseguire l'operazione. Riprova pi tardi.
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