| A Sub-mW Fractional- ADPLL With FOM of −246 dB for IoT Applications H Liu, D Tang, Z Sun, W Deng, HC Ngo, K Okada IEEE Journal of Solid-State Circuits 53 (12), 3540-3552, 2018 | 57 | 2018 |
| A 0.98 mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of− 246dB for IoT applications in 65nm CMOS H Liu, D Tang, Z Sun, W Deng, HC Ngo, K Okada, A Matsuzawa 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 246-248, 2018 | 49 | 2018 |
| A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration B Liu, Y Zhang, J Qiu, HC Ngo, W Deng, K Nakata, T Yoshioka, J Emmei, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 603-616, 2020 | 33 | 2020 |
| 8.5 A 0.42 ps-jitter− 241.7 dB-FOM synthesizable injection-locked PLL with noise-isolation LDO HC Ngo, K Nakata, T Yoshioka, Y Terashima, K Okada, A Matsuzawa 2017 IEEE International Solid-State Circuits Conference (ISSCC), 150-151, 2017 | 33 | 2017 |
| A 1.2 ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ... 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018 | 20 | 2018 |
| A 0.4-ps-jitter− 52-dBc-spur synthesizable injection-locked PLL with self-clocked nonoverlap update and slope-balanced subsampling BBPD B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ... IEEE Solid-State Circuits Letters 2 (1), 5-8, 2019 | 13 | 2019 |
| A 56-Gb/s PAM4 transceiver with false-lock-aware locking scheme for mueller-müller CDR F Tachibana, HC Ngo, G Urakawa, T Toi, M Ashida, Y Tsubouchi, ... ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022 | 4 | 2022 |
| Large-message size allreduce at wire speed for distributed deep learning K Tanaka, Y Arikawa, K Kawai, J Kato, T Ito, HC Ngo, K Morita, F Miura, ... Poster session presented at SC18, and Analysis, 2018 | 4 | 2018 |
| Distributed Deep Learning System and Data Transfer Method K Tanaka, Y Arikawa, K Kawai, J Kato, T Ito, H Ngo, T Sakamoto US Patent App. 17/291,082, 2021 | 3 | 2021 |
| Distributed Deep Learning System J Kato, K Kawai, H Ngo, Y Arikawa, T Ito, T Sakamoto US Patent App. 16/979,066, 2021 | 3 | 2021 |
| Distributed Deep Learning System J Kato, K Kawai, H Ngo, Y Arikawa, T Ito, T Sakamoto US Patent App. 16/967,702, 2021 | 2 | 2021 |
| Inference Processing Apparatus and Inference Processing Method H Ngo, Y Arikawa, T Sakamoto US Patent App. 17/615,610, 2022 | 1 | 2022 |
| Inference processing device and inference processing method H Ngo, Y Arikawa, T Sakamoto, Y Kishino US Patent App. 17/293,736, 2021 | 1 | 2021 |
| A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-based PAM4 Transceiver F TACHIBANA, HCU NGO, G URAKAWA, T TOI, M ASHIDA, ... IEICE Transactions on Fundamentals of Electronics, Communications and …, 2024 | | 2024 |
| Distributed processing system and distributed processing method T Ito, K Kawai, J Kato, H Ngo, Y Arikawa, T Sakamoto US Patent 11,823,063, 2023 | | 2023 |
| Distributed Deep Learning System and Data Transfer Method K Tanaka, Y Arikawa, K Kawai, J Kato, T Ito, H Ngo, T Sakamoto US Patent App. 17/775,549, 2022 | | 2022 |
| Inference Processing Apparatus and Inference Processing Method H Ngo, Y Arikawa, T Sakamoto US Patent App. 17/615,945, 2022 | | 2022 |
| Distributed Deep Learning System T Ito, K Kawai, J Kato, H Ngo, Y Arikawa, T Sakamoto, K Tanaka US Patent App. 17/627,346, 2022 | | 2022 |
| Distributed Processing System and Distributed Processing Method K Kawai, J Kato, H Ngo, Y Arikawa, T Sakamoto US Patent App. 17/596,070, 2022 | | 2022 |
| Distributed Deep Learning System Y Arikawa, K Kawai, J Kato, H Ngo, T Ito, K Tanaka, T Sakamoto US Patent App. 17/614,829, 2022 | | 2022 |
Bangan LiuNvidia CorporationVerified email at nvidia.com
Bangan LiuNvidia CorporationVerified email at nvidia.com