| CNTFET-based design of ternary logic gates and arithmetic circuits S Lin, YB Kim, F Lombardi IEEE transactions on nanotechnology 10 (2), 217-225, 2009 | 638 | 2009 |
| A novel CNTFET-based ternary logic gate design S Lin, YB Kim, F Lombardi 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 435-438, 2009 | 206 | 2009 |
| Design of a ternary memory cell using CNTFETs S Lin, YB Kim, F Lombardi IEEE transactions on nanotechnology 11 (5), 1019-1025, 2012 | 168 | 2012 |
| Design of a CNTFET-based SRAM cell by dual-chirality selection S Lin, YB Kim, F Lombardi IEEE Transactions on Nanotechnology 9 (1), 30-37, 2009 | 125 | 2009 |
| Analysis and design of nanoscale CMOS storage elements for single-event hardening with multiple-node upset S Lin, YB Kim, F Lombardi IEEE Transactions on Device and Materials Reliability 12 (1), 68-77, 2011 | 121 | 2011 |
| Design and performance evaluation of radiation hardened latches for nanoscale CMOS S Lin, YB Kim, F Lombardi IEEE transactions on very large scale integration (VLSI) systems 19 (7 …, 2010 | 97 | 2010 |
| A new SRAM cell design using CNTFETs S Lin, YB Kim, F Lombardi, YJ Lee 2008 International SoC Design Conference 1, I-168-I-171, 2008 | 85 | 2008 |
| Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability S Lin, YB Kim, F Lombardi Integration 43 (2), 176-187, 2010 | 83 | 2010 |
| A 11-transistor nanoscale CMOS memory cell for hardening to soft errors S Lin, YB Kim, F Lombardi IEEE transactions on very large scale integration (VLSI) systems 19 (5), 900-904, 2010 | 77 | 2010 |
| Soft-error hardening designs of nanoscale CMOS latches S Lin, YB Kim, F Lombardi 2009 27th IEEE VLSI Test Symposium, 41-46, 2009 | 62 | 2009 |
| A low leakage 9T SRAM cell for ultra-low power operation S Lin, YB Kim, F Lombardi Proceedings of the 18th ACM Great Lakes symposium on VLSI, 123-126, 2008 | 62 | 2008 |
| A highly-stable nanometer memory for low-power design S Lin, YB Kim, F Lombardi 2008 IEEE International Workshop on Design and Test of Nano Devices …, 2008 | 38 | 2008 |
| A 32nm SRAM design for low power and high stability S Lin, YB Kim, F Lombardi 2008 51st Midwest Symposium on Circuits and Systems, 422-425, 2008 | 36 | 2008 |
| A novel design technique for soft error hardening of Nanoscale CMOS memory S Lin, YB Kim, F Lombardi 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 679-682, 2009 | 16 | 2009 |
| Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset S Lin, YB Kim, F Lombardi 2011 IEEE 29th International Conference on Computer Design (ICCD), 320-325, 2011 | 8 | 2011 |
| Read-out schemes for a CNTFET-based crossbar memory S Lin, YB Kim, F Lombardi Proceedings of the 20th symposium on Great lakes symposium on VLSI, 167-170, 2010 | 5 | 2010 |
| A novel hardened design of a cmos memory cell at 32nm S Lin, YB Kim, F Lombardi 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2009 | 4 | 2009 |
| A PVT Tolerant Low Leakage and Highly Stable 9 Transistor 32nm CMOS SRAM Cell S Lin IEEE Transactions on Very Large Scale Integration Systems http …, 2008 | 4 | 2008 |
| Analysis and design of robust storage elements in nanometric circuits S Lin Northeastern University, 2011 | 3 | 2011 |
| A 13T CMOS Memory Cell for Multiple Node Upset Hardening at 32nm S Lin, YB Kim, F Lombardi | | |
Yong-Bin KimNortheastern University, University of Utah, SUN Microsystems, HP, IntelVerified email at ece.neu.edu
